Document Type and Number:
Japanese Patent JPS6334481
Kind Code:
B2
Abstract:
A control loop provided with a control unit for realizing a transfer characteristic having a number of peaks at a fundamental frequency and harmonics thereof. The control unit comprises a memory device for digitally storing a number of samples of the error signal appearing in the control loop during a cycle period equal to the period corresponding to the fundamental frequency. Furthermore, there are provided means for comparing the sample stored in the memory device with the value of the error signal one cycle period later and, depending on this comparison, correcting the memory content of the relevant memory location. The variation of the error signal stored in the memory device is furthermore cyclically employed as a control signal for the control device included in the control loop.
Inventors:
KORUNERISU ANTONII IMINKU
ABURAHAMU HOOHENDOORUN
ABURAHAMU HOOHENDOORUN
Application Number:
JP2680480A
Publication Date:
July 11, 1988
Filing Date:
March 05, 1980
Export Citation:
Assignee:
FUIRITSUPUSU FURUUIRANPENFUABURIKEN NV
International Classes:
G11B5/58; G05B5/01; G05B11/36; G05B21/02; G11B7/08; G11B7/09; G11B21/03; G11B21/10
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