Document Type and Number:
Japanese Patent JPS6351572
Kind Code:
B2
Abstract:
PURPOSE:To stably and accuratly obtain a frequency locked at a fraction of integer by frequency-dividing a reference clock frequency with a frequency controlling signal. CONSTITUTION:The 1st-3rd frequency control signals Vincr, Vupper, and Vlower are inputted to input terminals of an adder 1, a comparator 2 and a switch 3. Depending whether an output signal Va of the adder 1 is larger or smaller than the Vupper, the 1st or 2nd input terminal of the switch 3 is changed over. A sample and hold circuit 4 samples an input voltage just before the rise of a clock and outputs the sampling result as an output voltage just after the rise. Even if the signals Vincr, Vupper, and Vlower are more or less unstable and have an error, the output frequency is completely synchronized with the clock frequency. The two signals out of the three signals can be fixed voltages.
Inventors:
YAMADA KUNIHIRO
Application Number:
JP17190081A
Publication Date:
October 14, 1988
Filing Date:
October 27, 1981
Export Citation:
Assignee:
RIKOO KK
RIKOO EREMETSUKUSU KK
RIKOO EREMETSUKUSU KK
International Classes:
H03K4/02; H03B19/00; H03K3/02