Document Type and Number:
Japanese Patent JPS6352247
Kind Code:
B2
Abstract:
A sequencing logic circuit comprises a blocking means for preventing phase jumps caused by the untimely presence of a release signal. An inhibitor device is placed on one of the channels feeding a storage relay, placed upstream of said release signal, in such a manner as to prevent the transmission thereto of a pressure for placing it in logic state "1." This inhibitor device is actuated by the release signal and does not permit any communication between the latter and the channel controlled.
Inventors:
DANIERU BUTEIIYU
MITSUSHERU DEYUKURO
YUUGE MARUGE
MITSUSHERU NIKORASU
ERITSUKU PETORIMOO
MITSUSHERU DEYUKURO
YUUGE MARUGE
MITSUSHERU NIKORASU
ERITSUKU PETORIMOO
Application Number:
JP2401279A
Publication Date:
October 18, 1988
Filing Date:
March 01, 1979
Export Citation:
Assignee:
RA TEREMEKANITSUKU EREKUTORITSUKU SA
International Classes:
F15B21/12; F15C3/04; F15C4/00; G05B19/44
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