Document Type and Number:
Japanese Patent JPS6353735
Kind Code:
B2
Abstract:
PURPOSE:To obtain a logic circuit having a large noise tolerance, by using the antiphase output of the 1st currnet change-over type logic circuit for the reference voltage of the 2nd current change-over type logic circuit and the antiphase output of the 2nd logic circuit for the reference voltage of the 1st logic circuit each. CONSTITUTION:The 1st and 2nd logic circuit G1 and G2 consisting of transistors TRQ1 and Q2 plus TRQ3 and Q4 each receive input signal IN. The antiphase output VR2 of G1 is applied to TRQ4 in the form of the reference voltage of circuit G2; and the antiphase output VR1 of G2 is applied to TRQ2 in the form of the reference voltage of G1 respectively. Then the value of resistance R2 is selected so that the amplitude of the antiphase output of G1 may be half of the amplitude of signal IN. As a result, a logic circuit having a large noise tolerance can be obtained regardless of the level of the input signal.
Inventors:
ASO AKIRA
KIMURA HIROMICHI
KIMURA HIROMICHI
Application Number:
JP8189979A
Publication Date:
October 25, 1988
Filing Date:
June 28, 1979
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H03K3/0233; H03K19/018; H03K19/086