Document Type and Number:
Japanese Patent JPS639694
Kind Code:
B2
Abstract:
A PCM signal interface apparatus comprises a buffer memory being capable of asynchronously writing and reading a PCM signal, means for inserting a frame marker to the PCM signal upon writing the PCM signal into the buffer memory, means for judging whether or not the frame marker is contained in an output signal read out of the buffer memory at a time that is designated by an external read frame position designating pulse, means for resetting all the contents in the buffer memory and temporarily stopping the supply of a writing clock and a reading clock to the buffer memory when the frame marker is not delivered out at the predetermined time, means for resuming the supply of the writing clock to the buffer memory by receiving a write frame position designating pulse, and means for resuming the supply of the reading clock to the buffer memory by receiving the frame position designating pulse at a predetermined time lapse after the resumption of the writing clock supply. The data written into the buffer memory can be read out at a desired frame phase and data speed without duplication and missing of the read data.
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Inventors:
MARUTA RIKIO
Application Number:
JP6401680A
Publication Date:
March 01, 1988
Filing Date:
May 16, 1980
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H04J3/06; H04J3/12; H04J4/00; H04L7/08
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