Title:
メモリ制御装置及びメモリ制御方法
Document Type and Number:
Japanese Patent JPWO2006132006
Kind Code:
A1
Abstract:
アクセス回路30,40から発行されたアクセス要求を調停回路20で調停して記憶装置10にアクセスする一方、アクセス回路30,40から発行されたアクセス要求を調停回路21で調停して記憶装置11にアクセスする。
Inventors:
Takuto Tanaka
Tetsuji Mochida
Tetsuji Mochida
Application Number:
JP2007520026A
Publication Date:
January 08, 2009
Filing Date:
December 26, 2005
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G06F12/00
Domestic Patent References:
JP2003263363A | 2003-09-19 | |||
JP2002500395A | 2002-01-08 | |||
JP2000132503A | 2000-05-12 | |||
JPS61256458A | 1986-11-14 | |||
JPS63175964A | 1988-07-20 | |||
JPH01231145A | 1989-09-14 | |||
JP2000187615A | 2000-07-04 | |||
JPH01169565A | 1989-07-04 | |||
JPH03212754A | 1991-09-18 |
Foreign References:
WO2004029816A2 | 2004-04-08 |
Attorney, Agent or Firm:
Hiroshi Maeda
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori
Seki Kei
Yasuya Sugiura
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori
Seki Kei
Yasuya Sugiura
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