Document Type and Number:
Japanese Patent JPWO2022190329
Kind Code:
A1
Abstract:
A prior-art communication system has a problem that it takes a lot of trouble to detect an error in a control/user plane and to analyze the error. A protocol analyzer according to the present invention includes: a protocol check circuit (11) that while detecting an error in a control plane and a user plane, relays the control plane and the user plane between a radio unit (20) and a baseband unit (30); and a fault detection packet generation unit (12) that generates a fault detection packet on the basis of error cause information, an ether header, and a time stamp that are generated by the protocol check circuit (11) in response to detection of an error in the control plane and the user plane. The protocol check circuit (11) interprets the control plane and the user plane on the basis of information on a management plane that determines transmission-reception conditions of the control plane and the user plane between the radio unit (20) and the baseband unit (30).
Application Number:
JP2023505021A
Publication Date:
September 15, 2022
Filing Date:
March 11, 2021
Export Citation:
