DRIVE CIRCUIT AND METHOD FOR SEMICONDUCTOR DEVICES

CROSS-REFERENCE TO RELATED APPLICATION [0001] The present application claims priority from:

• U.S. Patent Application No. 11/751,615, filed May 21, 2007 for "Drive Circuit and Method for Semiconductor Devices" (inventor Robert E. Godes), and

• U.S. Patent Application No. 11/419,671, filed May 22, 2006 for "Drive Circuit and Method for Semiconductor Devices" (inventor Robert E. Godes), the entire disclosures of which are incorporated by reference.

BACKGROUND OF THE INVENTION [0002] The present invention relates generally to power semiconductor devices, and more specifically to techniques for driving the gate of large power devices such as power MOSFETs and insulated gate bipolar transistors (IGBTs).

[0003] The operation of a power MOS device entails rapid charging and discharging of the gate to cause transitions through the device's linear region between its fully enhanced ("on") and fully shut off ("off ) states. Typical gate drive circuit technology applies a DC voltage to the device gate to charge and discharge the gate and thus change the device state. This gate voltage is chosen to be above the full enhancement voltage but below the maximum gate voltage. Reference to the gate voltage or voltage on the gate is normally the voltage relative the source (if the device is an FET), or relative to the emitter (if the device is an IGBT).

[0004] The power dissipation of the device is reasonably given by the product of drain- source current and drain-source voltage. When the device is in its off state, the drain-source voltage is significant, but there is substantially no drain-source current, and the dissipation is extremely low. Similarly, when the device is in its on state, the drain-source current is significant, but the drain-source voltage is substantially zero, and the dissipation is extremely low. However, when the device is passing through its linear state, the drain-source current is increasing/decreasing and drain-source voltage is decreasing/increasing (depending on the direction of the transition). During this time, power is being dissipated.

[0005] Thus, it is a well-known goal to improve the switching speed, but like many well- known goals, it is easier the than done. The ability to rapidly charge and discharge the gate is impeded by a number of factors, including one or more of the following: (a) inductance and

resistance introduced by the package and system interconnect; (b) the Miller effect (the tendency of a capacitance to be multiplied by the gain of adjacent stages in a electrical circuit); and (c) source and drain inductance.

[0006] For a given voltage applied to the gate drive point of the device to be switched, the speed at which the gate voltage can change is limited by the complex impedance, including offsets, of the circuit, even if the gate driver has zero impedance. However, using a larger steady-state drive voltage to overcome the complex impedance of the switching system and increase the switching speed would destroy the device being switched as soon as the charge on the gate exceeded the maximum allowable charge for the device.

SUMMARY OF THE INVENTION

[0007] In short, the present invention is able to overcome many of the speed limitations of switching a gated device while protecting the device from damage.

[0008] In one aspect of the invention, this is accomplished by providing a dynamic driving voltage to the gate of the device being switched. This dynamic voltage provides a way to overcome the complex impedances between the drive point and the actual gate allowing faster switching speeds, preferably while still allowing a resistance in series with the gate to dampen out ringing (this damping resistance is provided by a bilateral switch used to hold the device in the desired state.). Embodiments of the invention provide this dynamic driving voltage by starting with a fixed amount of charge at a higher initial potential. The fixed charge and voltage are chosen so as not to exceed the device's specified maximum gate current or the device's maximum voltage between the gate and the source (punch-through voltage).

[0009] Embodiments of the invention provide techniques for switching a semiconductor device between first and second device states by controlling the charge on a gate associated with the device. The first and second device states are characterized by first and second voltages on the gate, with the first voltage being higher than the second voltage. For an n- channel device, the first and second device states would be ON and OFF states, respectively, while for a p-channel device, the first and second device states would be OFF and ON states, respectively.

[0010] Embodiments of the invention use a capacitor that is charged by a voltage supply to a voltage (third voltage) that is significantly higher than the voltage (e.g., the first voltage) to which the device gate is subjected. The capacitor and the voltage source together define a

charge amount that, when transferred to the gate, results in a voltage on the gate that is commensurate with the first voltage so as to cause the semiconductor device to enter the first device state. The charge is supplied to a circuit node coupled to the gate with a time behavior characterized by a sufficiently high initial voltage to overcome a complex impedance that exists between the circuit node and the gate.

[0011] In specific examples, a device transition occurs with a positive voltage on the gate, and the third voltage is a relatively large positive voltage. However, for ease of nomenclature, a statement that a voltage is higher than another should be understood to cover a case of a negative voltage whose absolute voltage value is greater than that of the other voltage.

[0012] Another aspect of the invention provides a circuit comprising a voltage source supplying a third voltage that is significantly higher than the first voltage, a charge storage device, switching circuitry for selectively connecting the charge storage device to the voltage source, and control circuitry, coupled to the switching circuitry and responsive to an input signal.

[0013] When the input signal signifies a transition to the first device state, the switching circuitry connects the voltage source to the charge storage device, and the charge storage device transfers an amount of charge characteristic of the charge storage device and the voltage source to the gate. The charge storage device and the third voltage are chosen so that the voltage on the gate, after the amount of charge is transferred to the gate, is commensurate with the first voltage so as to cause the semiconductor device to enter the first device state, and the charge is supplied to a circuit node coupled to the gate with a time behavior characterized by a sufficiently high initial voltage to overcome a complex impedance that exists between the circuit node and the gate.

[0014] Some embodiments use first and second capacitors, which are selectively connected to the circuit node after being charged by connection to respective voltage sources (one for charging and one for discharging). Other embodiments use a single capacitor that is always connected to the circuit node, and the charge transfer occurs when the other side of the capacitor is selectively coupled to the voltage source.

[0015] Another aspect of the invention provides a circuit comprising a voltage source supplying a third voltage that is significantly higher than the first voltage, a charge storage device having first and second nodes with the first node connected to a circuit node coupled

to the gate, switching circuitry for selectively connecting the second node of the charge storage device to the voltage source, and control circuitry, coupled to the switching circuitry and responsive to an input signal.

[0016] When the input signal signifies at transition to the first device state, the switching circuitry connects the voltage source to the second node of the charge storage device, and the charge storage device transfers an amount of charge characteristic of the charge storage device and the voltage source to the gate. The charge storage device and the third voltage are chosen so that the voltage on the gate, after the amount of charge is transferred to the gate, is commensurate with the first voltage so as to cause the semiconductor device to enter the first device state, and the charge is supplied to the circuit node coupled to the gate with a time behavior characterized by a sufficiently high initial voltage to overcome a complex impedance that exists between the circuit node and the gate.

[0017] Another aspect of the invention provides a method comprising providing a voltage source supplying a third voltage that is significantly higher than the first voltage, providing a charge storage device having first and second nodes with the first node connected to a circuit node coupled to the gate, in response to an input signal specifying a transition from the second device state to the first device state, connecting the second node of the charge storage device to the voltage source, and transferring an amount of charge characteristic of the charge storage device and the voltage source to the gate. The charge storage device and the third voltage are chosen so that the voltage on the gate, after the amount of charge is transferred to the gate, is commensurate with the first voltage so as to cause the semiconductor device to enter the first device state, and the charge is supplied to the circuit node coupled to the gate with a time behavior characterized by a sufficiently high initial voltage to overcome a complex impedance that exists between the circuit node and the gate..

[0018] The method may also include, in response to an input signal specifying a transition from the first device state to the second device state, connecting the second node of the charge storage device to an additional voltage source, which may be ground or negative, but not necessarily of large absolute value.

[0019] Another aspect of the invention provides a circuit comprising a first voltage source, a first charge storage device, first switching circuitry, second switching circuitry, and control circuitry. The first voltage source supplies a third voltage that is significantly higher than the first voltage, and the first switching circuitry selectively connects the first charge storage

device to the first voltage source. The second switching circuitry selectively connects the first storage device to the gate. The control circuitry is coupled to the first and second switching circuitry and is responsive to an input signal to establish first and second circuit states.

[0020] When the circuit enters the first circuit state, the first switching circuitry connects the first voltage source to the first charge storage device while the second switching circuitry isolates the first charge storage device from the gate. This causes the first storage device to be charged to the third voltage.

[0021] When the circuit enters the second circuit state, the first switching circuitry isolates the first voltage source from the first charge storage device while the second switching circuitry connects the first charge storage device to the gate, whereupon the first charge storage device transfers a significant portion of its charge to the gate. The capacity of the first charge storage device and the third voltage are chosen so that the voltage on the gate, after the charge transfer, is commensurate with the first voltage so as to cause the semiconductor device to enter the first device state. This results in very rapid switching from the first state to the second state.

[0022] Some embodiments include additional elements to hold the gate at the first voltage after the first charge storage device has transferred a significant portion of its charge to the gate. These include a voltage source supplying a voltage equal to the second voltage, and switching circuitry for selectively coupling the gate to the voltage source while the second switching circuitry again isolates the first charge storage device from the gate.

[0023] Some embodiments include additional elements to effect rapid switching from the second state to the first state. These include a second voltage source supplying a fourth voltage that is significantly lower than the second voltage, a second charge storage device, third switching circuitry for selectively connecting the second charge storage device to the second voltage source, and fourth switching circuitry for selectively connecting the second storage device to the gate. The control circuitry establishes circuit states where the second storage device is charged to the fourth voltage and where the gate rapidly transfers a significant portion of its charge to the second storage device.

[0024] Another aspect of the invention provides a method comprising: charging a first capacitor to a third voltage that is significantly higher than the first voltage while keeping the first capacitor decoupled from the gate; and thereafter, connecting the first capacitor to the

gate so that the first capacitor transfers a significant portion of its charge to the gate. The first capacitor and the third voltage are chosen so that the voltage on the gate, after the charge transfer, is commensurate with the first voltage so as to cause the device to enter the first state.

[0025] Some embodiments include additional steps to effect rapid switching from the second state to the first state. These include charging a second capacitor to a fourth voltage that is significantly lower than the second voltage while keeping the second capacitor decoupled from the gate; and thereafter, connecting the second capacitor to the gate so that the gate transfers a significant portion of its charge to the second capacitor. The second capacitor and the fourth voltage are chosen so that the voltage on the gate, after the charge transfer, is commensurate with the second voltage so as to cause the device to enter the second state.

[0026] A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG. 1 is a high-level block diagram of a gate drive circuit according to a first embodiment of the present invention;

[0028] FIG. 2 A and FIG. 2B provide a state transition diagram of the gate drive circuit of FIG. 1;

[0029] FIG. 3 A is a circuit schematic of the portions of the gate drive circuit of FIG. 1 that are responsible for rapidly charging (turning on) the gate;

[0030] FIG. 3B is a circuit schematic of the portions of the gate drive circuit of FIG. 1 that are responsible for rapidly discharging (turning off) the gate; and

[0031] FIG. 4 is a simplified timing diagram for the gate drive circuit of FIG. 1, showing the voltages on the gate-charging and gate-discharging capacitors and on the gate node, referenced to the differential signal derived from the logic input signal for the gate drive circuit of FIG. 1;

[0032] FIG. 5 is a high-level block diagram of a gate drive circuit according to a second embodiment of the present invention;

[0033] FIG. 6A and FIG. 6B provide a state transition diagram of the gate drive circuit of FIG. 5;

[0034] FIG. 7A is a circuit schematic of the portions of the gate drive circuit of FIG. 5 that are responsible for rapidly charging (turning on) and rapidly discharging (turning off) the gate;

[0035] FIG. 7B is a circuit schematic of the portions of the gate drive circuit of FIG. 5 that are responsible for holding the gate on and off after the gate has been charged and discharged; and

[0036] FIG. 8 is a simplified timing diagram for the gate drive circuit of FIG. 5, showing the voltages on the gate-charging/discharging capacitor and on the gate node, referenced to the differential signal derived from the logic input signal.

DESCRIPTION OF SPECIFIC EMBODIMENTS Introduction [0037] Embodiments of the present invention provide circuits and methods for rapidly switching gated semiconductor devices. Two embodiments are described below. The first embodiment is described with reference to FIG. 1 through FIG. 4 while the second embodiment is described with reference to FIG. 5 through FIG. 8. The specific cases described are where a positive voltage on the gate causes the device to change state and a larger positive voltage is used to speed up the transition. However, it is contemplated that there may be instances where a negative voltage is used to cause the state change and a more negative voltage is used to speed up the transition. For ease of nomenclature, a statement that a voltage is higher than another should be understood to cover a case of a negative voltage whose absolute voltage value is greater than that of the other voltage.

First Embodiment — Circuit Overview [0038] FIG. 1 is a high-level block diagram of a gate drive circuit 10 according to the first embodiment of the present invention. In short, circuit 10 responds to a signal at a Logic ln input 15 and drives the gate node (terminal) 20 of a semiconductor device 25 (often referred to simply as "the device") in response to that signal. The device may be a field effect transistor (FET) or an insulated gate bipolar transistor (IGBT). The device is shown as having two additional nodes (terminals) 30 and 32. Terminal 30 is shown connected to

ground while terminal 32 is shown connected to one terminal of a load 40, the other terminal of which is connected to a voltage supply 45 (V LOAD)-

[0039] As mentioned above, a number of factors limit the rate at which the device gate can be charged. These include the Miller Effect, and various inductances (e.g., drain, source, package, and interconnect). As will be described in detail below embodiments of the present invention charge the gate more quickly by using a larger initial voltage to start current flow, thus mitigating the above factors.

[0040] The drawing illustrates, at a high level, the notion that the terminals seen by the gate drive circuit are coupled via communication paths to corresponding structures of the actual semiconductor device (the "device proper"), which is designated 25a. The gate drive circuit is designed to turn the actual device gate on and off by supplying suitable voltages to the gate node on the device package. The communication paths are shown in dashed lines, and the device gate, source, and drain (for a MOSFET) are shown schematically as hollow circles.

[0041] The gate will sometimes be referred to as the gate proper to distinguish it from gate node 20. The dashed paths are the source of complex impedances that limit the rate at which a voltage change at gate node 20 is communicated to the gate proper to charge or discharge the gate proper. The distinction between the gate node and the gate proper is significant in some contexts and not others. The distinction is most significant since the gate drive circuit applies an initial voltage to the gate terminal that is larger than could be safely applied to the gate proper.

[0042] Circuit 10 is shown as having a supply voltage V _Q C and ground. The device is characterized by a full enhancement voltage, i.e., the gate voltage required to turn the device fully on, and V _cc will typically be chosen to be slightly above (say a volt or two above) the device's full enhancement voltage. In some instances, gate turn-off is accomplished by applying a voltage, designated V _GATEOFF , below the source voltage (ground), which can be provided by an optional bias source 35. The use of galvanic isolation in this section allows the use of an optional bias source to provide negative gate bias commonly used in high voltage FET and IGBT circuits.

[0043] If the device is an FET, terminals 30 and 32 are the source and drain, while if the device is an IGBT, terminals 30 and 32 are the emitter and collector. For convenience, the remaining description will be in terms of an n-channel MOSFET where the source is

connected to ground, voltage supply 45 provides a positive voltage, and the MOSFET is turned on by a positive voltage applied to the gate proper via gate node 20. When a voltage on the order of V _cc is applied to the gate, the device is turned on; when the gate is at ground

(or the optional negative bias voltage), the device is off. It will be understood, however, that in the case of p-channel devices, a positive gate voltage will turn the device off, while a zero or negative gate voltage will turn the device on.

[0044] Circuit 10 comprises a number of subsystems as will be outlined below. In short, circuit 10 uses a pair of capacitors 50(ChargeGate) and 50(DischargeGate) to rapidly charge and discharge the gate. The capacitors are selectively precharged by respective positive and negative voltage supplies 55P and 55N, which provide voltages that are significantly higher in absolute value than other characteristic voltages in the system. This is accomplished by a number of controlled switch blocks, each of which is shown schematically as including a control block and a switch. A reference to a block being turned on or off should normally be interpreted to mean that the switch within that block is being turned on or off.

[0045] The voltages on supplies 55P and 55N are referred to as PositiveFlush and

NegativeFlush, respectively, and are typically higher in absolute value than the maximum voltage that the gate can withstand. However, the capacitor values are chosen so that the total charge on the capacitors is sufficiently small that when the charge is transferred to/from the gate, the voltage on the gate will be within the levels that the device can tolerate. The particular voltage values and capacitor values are chosen in view of the packaging and interconnect, and the absolute voltage value can vary, say between several 10's of volts to more than 1000V. For example, if the circuit must be mounted far from the actual device, this may require a very small capacitor with a very high voltage to overcome the inductance but not overshoot the target value for the gate voltage.

[0046] A level translation circuit 60, which may include a Schmitt trigger, receives the signal at Logic In input 15 and generates a representation of that signal translated from logic levels to gate drive levels. The level translation circuit preferably also provides better defined edges. The representative signal is provided as a pair of complementary signals D and D/. D assumes one of V _cc and ground (actually a voltage that is slightly above ground by a saturation voltage of a transistor), and D/ assumes the other. The other elements in circuit 10 use these signals to charge and discharge gate 20 much faster than the characteristic

rise and fall times of the D and D/ signals. In down-to-earth terms, the circuit sharpens a rather dull edge to a knife edge to charge and discharge the gate.

[0047] A switch block 70(precharge +), when turned on, connects capacitor 50(ChargeGate) to supply 55P to permit precharging of the capacitor to the voltage on supply 55P. A switch block 70(precharge -), when turned on, connects capacitor 50(DischargeGate) to supply 55N to permit precharging of the capacitor to the voltage on supply 55N.

[0048] A switch block 80(ChargeGate), when turned on, connects capacitor 50(ChargeGate) to gate 20 to permit charging the gate. As will be described below, capacitor 50(ChargeGate), while charged to the high voltage on supply 55P (e.g., +100V), does not expose the gate to this voltage; to do so would cause punch-through. Rather, the capacitor is sufficiently small so that the amount of charge, when transferred to the gate, charges the gate to a voltage that is sufficient for a full turn-on (say a voltage on the order of V _cc ). Similarly, a switch block 80(DischargeGate), when turned on, connects capacitor 50(DischargeGate) to gate 20 to permit discharging the gate to the capacitor. Again, capacitor 50(DischargeGate), while charged to the high absolute- value voltage on supply 55N (e.g., -100V), does not expose the gate to this voltage.

[0049] A switch block 90(HoldGateOn), when turned on, provides a low-impedance path between gate node 20 and V _cc . Similarly, a switch block 90(HoldGateOff), when turned on, provides a low-impedance path between gate node 20 and ground. These switch blocks ensure stable levels on the gate between transitions, although this might be unnecessary in some situations where the gate, once charged or discharged, remains in that state in the absence of intervention. Thus these switch blocks should be considered preferred rather than necessary.

First Embodiment — State Changes [0050] FIG. 2 A and FIG. 2B provide a state transition diagram of circuit 10 and device 25. The reasons for the state transitions in response to specific triggering events will not be described at this point, but will become clear in view of a later description of the circuitry in a particular embodiment. FIG. 2A shows the states and state transitions while FIG. 2B shows schematically the states of the switching blocks in each state. In an initial state 100 before power is applied to the system, there is no charge on any of the capacitors and device 25 is off. All the switch blocks are off (this state is not shown in FIG. 2B).

[0051] When power is turned on, the system transitions to a state 110 where the voltage supplies reach their designated voltages (Vcc, PositiveFlush, and NegativeFlush), the device and the blocks remain off, and neither capacitor is charged. However, Logic_In is low, which means that D is low and D/ is high.

[0052] This causes a transition to a state 120 where switch blocks 70(precharge +) and 90(HoldGateOff) are turned on. Turning on switch block 70(precharge +) starts the charging of capacitor 50; turning on switch block 90(HoldGateOff) holds the gate at ground and keeps the device off.

[0053] When Logic ln goes high, the system transitions to a state 130 where switch blocks 70(precharge +) and 90(HoldGateOff) are turned off, thereby stopping the charging of capacitor 50(ChargeGate) and decoupling the gate from ground. This transition then turns switch block 80(ChargeGate) on. The initially high voltage at gate node 20 overcomes the complex impedances between the gate node and the gate proper. This allows a high current charge transfer from capacitor 50(ChargeGate) to the gate, but the high voltage at the gate node decays without being seen by the gate. Switch block 70(precharge -) is also turned on to commence charging capacitor 50(DischargeGate) in preparation for the next time Logic_In goes low. At some point during the discharge of capacitor 50(ChargeGate) in state 130, the voltage on the capacitor has fallen below a certain level (about two diode drops below V _cc in the specific embodiment) and the gate is sufficiently charged to turn device 25 on.

[0054] The drop in the voltage on capacitor 50(ChargeGate) causes a transition to a state 140 where switch block 80(ChargeGate) turns off and switch block 90(HoldGateOn) turns on, which provides a low impedance path between the gate and V _cc to keep the gate charged and keep the device on.

[0055] When Logic_In goes low, the system transitions to a state 150 where switch blocks 90(HoldGateOn) and 70(precharge -) are turned off, thereby stopping the charging of capacitor 50(DischargeGate) and decoupling the gate from V _cc . Thereafter switch block

80(DischargeGate) is turned on. This allows a high current charge transfer from the gate to capacitor 50(DischargeGate). Switch block 70(precharge +) is also turned on to commence charging capacitor 50(ChargeGate) in preparation for the next time Logic_In goes low.

[0056] A delayed response to Logic ln going low, timed to allow completion of the transfer of the gate charge to capacitor 50(DischargeGate), causes the circuit to transition

back to state 120, which was also entered in response to the initial Logic_In going low after power on.

[0057] It is noted that states 110, 120, 130, 140, and 150 are circuit states, which are different from the device ON and OFF states. In many instances, such as the description above, the context dictates whether a state that is referred to is a circuit state or a device state. In other contexts, it may be convenient to precede the mention of a state with the adjective "device" or "circuit" depending on the nature of the state being referred to.

First Embodiment — Circuit Details and Operation

[0058] FIG. 3A and FIG. 3B are circuit schematics showing a specific implementation of gate drive circuit 10 as shown in FIG. 1, with FIG. 3 A showing the portions of the gate drive circuit that are responsible for rapidly charging (turning on) the gate and FIG. 3B showing the portions of the gate drive circuit that are responsible for rapidly discharging (turning off) the gate.

[0059] FIG. 3 A shows level translation circuit 60, switch block 70(precharge +), switch block 80(ChargeGate), and switch block 90(HoldGateOn). In switch block 70(precharge +), a transistor Ql 8 is used to level shift and turn on a transistor Q8 after a small delay. Transistor Q8 is used to control the pre-charging of capacitor 50(ChargeGate). The pre- charging does not occur until capacitor 50(ChargeGate) has been discharged and the device is turning off.

[0060] A transistor Ql in switch block 80(ChargeGate) is used to trigger an SCR U2 through a diode D2, which protects transistor Ql from the rapid rise of the voltage at the gate of SCR U2 to the voltage on capacitor 50(ChargeGate). This occurs while the gate of the driven device's inductance fields form. A pair of transistors Q5 and Q6 in switch block 90(HoldGateOn), PMOS transistors in this specific embodiment, provide the low impedance connection to the gate holding voltage once capacitor 50(ChargeGate) has been discharged.

[0061] A pair of transistors Q9 and Q13 in switch block90(HoldGateOn) trigger SCR Ul once the voltage on capacitor 50(ChargeGate)is at V _cc minus the voltage drop across a diode

D8. A transistor Q4 turns off a transistor Ql 6 and then charges the gates of transistors Q5 and Q6. A transistor Ql 6 effects a fast turn off of transistors Q5 and Q6 and should be a high gain (hfe) transistor to limit power loss in a resistor Rl 9. The Vce seen by transistor Ql 6 never exceeds V _cc .

[0062] FIG. 3 B shows switch block 70(precharge -), switch block 80(DischargeGate), and switch block 90(HoldGateOff). Switch block 90(HoldGateOff) provides a low impedance path to the gate turn off voltage source. It is delayed by a biasing network on a transistor Q2, so as to allow switch block 80(DischargeGate) to complete the turn off of the device under control of the circuit. When transistor Q2 begins to conduct, it turns off a transistor Ql 7 and then charges the gates of transistors Ql 4 and Ql 5, NMOS transistors in this specific embodiment. Transistor Ql 7 effects a fast turn off of transistors Q14 and Ql 5 and should be a high gain (hfe) transistor to limit power loss in resistor R30. The Vce seen by transistor Ql 7 never exceeds V _cc .

[0063] Switch block 80(DischargeGate) is the control for the discharging of capacitor

50(DischargeGate) used to turn off the device under control of the circuit. When the control signal goes low, a transistor Q3 triggers an SCR U3 causing capacitor 50(DischargeGate) to remove the charge from the gate.

[0064] Switch block 70(precharge -) is the pre charging source for capacitor 50(DischargeGate). A transistor Q7 turns on a transistor Ql 9 with a small delay after the circuit begins to turn on the device under circuit control. Transistor Ql 9 precharges capacitor 50(DischargeGate) for the next turn off cycle.

[0065] FIG. 4 is a simplified timing diagram showing various voltages in the system. The bottom portion show the differential signal (D, D/) derived from the input signal at Logic ln input 15. The three portions starting from the top show the voltage on capacitor

50(ChargeGate), capacitor 50(DischargeGate), and the gate node. As noted above, when power is turned on, the voltage supplies reach their designated voltages (V co PositiveFlush, and NegativeFlush), the device and the blocks remain off, and neither capacitor is charged. However, Logic_In is low, which means that D is low and D/ is high. This initiates charging of capacitor 50(ChargeGate) to PositiveFlush and the gate being pulled down to the negative bias voltage V _QATE O _FF , if present, or the gate being held at ground.

[0066] The transition of D going high initiates a rapid transfer of charge from capacitor 50(ChargeGate) to the gate. This is made possible by the initially high voltage on the gate node. In the meantime, capacitor 50(DischargeGate) is being charged to the negative voltage NegativeFlush in preparation for the next transition of D going low, which initiates a rapid transfer of charge from the gate to capacitor 50(DischargeGate).

First Embodiment — Determining the Gate Drive Parameters

[0067] Once the characteristics of the switched semiconductor device are known, it is relatively straightforward to determine the values for capacitors 50(ChargeGate) and 50(DischargeGate), and the values for PositiveFlush and NegativeFlush.

[0068] Gated devices (FETs and IGBTs) are often described as voltage controlled but are actually charge controlled. The conductance of the device is more a function of the total charge on the gate, which is different from the voltage. As is well known, for linear devices such as capacitors, the capacitance, charge, and voltage are related by the equation V = Q / C (or equivalently, C = Q / V) where V is the voltage in volts, Q is the charge in coulombs, and C is the capacitance in farads. For gated devices, while the gate operates to store charge, it generally cannot be represented as a simple capacitor. Rather, complex impedances cause significant non-linearities in the voltage as a function of charge.

[0069] The actual maximum rate of change of charge on the gate of a device is not really known, as the best method of charging a gate to date has been to provide a very low impedance path to a voltage source at the desired final gate voltage. Some device designs have used a negative bias supply to help remove the tails of the turn off current but that still uses a DC voltage applied to the gate. For any given device there is a maximum gate current that the device can tolerate and a maximum voltage between the gate and the source that the device can tolerate without breaking down.

[0070] Thus, relevant device characteristics include:

• the full enhancement voltage, which is the gate voltage required to turn the device fully on;

• the full enhancement charge, which is the amount of charge required to turn the device fully on; • the gate punch-through voltage, which is the maximum voltage that the gate can withstand without breaking down;

• the maximum current that can be allowed to flow into or out of the gate without causing damage; and

• the gate impedance.

Of these quantities, the maximum current is not normally specified by the device manufacturer, but can be determined by testing the device

[0071] The analysis for charging the gate from capacitor 50(ChargeGate) will be discussed, it being understood that similar considerations apply to the discharging to capacitor 50(DischargeGate). For brevity, voltage PositiveFlush will be referred to as V++ and the value of capacitor 50(ChargeGate) will be referred to as C _CQ . AS mentioned above, in turning the device on, the gate will be driven to voltage V _cc , which is slightly (say a volt or two) above the full enhancement voltage but below the punch-through voltage. The desired value of charge on the gate will be referred to as Q _Q ATE-

[0072] Prior to transferring charge to the gate, the total charge on capacitor 50(ChargeGate) is C _CG *V++. If the gate were a simple capacitor, the result of transferring charge from capacitor 50(ChargeGate) to gate 20 would be to equalize the voltages on the capacitor and the gate at V _cc . However, power flow and inductance in the system will cause the final voltage on the capacitor to be less than V _cc and that fact is used to turn on SCR Ul . The capacitor will likely end up at a lower voltage due to inductance, and SCR Ul will prevent the backflow of charge to the capacitor and will be filtered back to the holding rail (V _cc ) through the bilateral holding switch defined by transistors Q5, Q6, and Ql 6.

[0073] Therefore, a reasonable approximation is as follows:

C _CG *V++ ^ QGATE (1)

Setting this constraint provides a safety margin and simplifies the calculation. More important to the user is the inductance between capacitor 50(ChargeGate) and the gate proper. This inductance will cause an additional amount of charge to be transferred to the gate. However the now lower voltage at gate node 20 provides negative feedback to quickly quench the curent spike in the actual device gate while block 90 transitions to the ON state.

[0074] This sets a constraint on C _CG and V++, but does not uniquely determine them. However, since it is desired to charge the gate as quickly as possible, V++ is preferably chosen so that the initial current INITIAL * ^S slightly below the device's maximum tolerable gate current value with appropriate device tolerance margin. If the system level gate impedance is Z,

V++ = IlNITIAL*Z (2) Substituting this into Equation 1 and rearranging leads to:

CcG ^~ QGATE / ( ¹ INITIAL* ² ) (3)

[0075] Consider the following possible example for a given device:

Note that V _QQ and QGATE ^aie not per se specified device characteristics, but rather are values that are based on the full enhancement voltage and the full enhancement charge. For example, the design choice of 12 volts for V _Q C ^m ight be based on a specified full enhancement voltage of 10 volts, i.e., 20% higher. While the gate is not a linear capacitor during the time it is being charged, it is a reasonable to assume a value for QGATE ^mat * ^{s a} l ^so higher than the full enhancement charge. Similarly, INITIAL * ^S chosen to be lower than the tested maximum current for the device.

[0076] Substituting the "device-dependent" values of INITIAL ^an d Z into Equation 2 leads to a value for V++ of (250 amps)*(l ohm) = 250 volts. Substituting this value, along with the "device-dependent" values of QGATE ^an & ^CC» ^mto Equation 3 leads to a value for C _CG of (2600 nanocoulombs) / (250 volts), or 10.4 nanofarads.

Second Embodiment — Circuit Overview

[0077] FIG. 5 is a high-level block diagram of a gate drive circuit 10' according to the second embodiment of the present invention. Elements in circuit 10' corresponding generally to those in circuit 10 of the first embodiment will be denoted by the same reference numbers, but primed. As with the first embodiment, circuit 10' responds to a signal at a Logic_In input 15 and drives gate node 20 of semiconductor device 25 in response to that signal. The comments regarding device 25 and its characteristics and operating environment made in connection with the description of the first embodiment will not be repeated here unless something differs by virtue of differences between the first and second embodiments.

[0078] Circuit 10' comprises a number of subsystems as will be outlined below. In short, circuit 10' differs from circuit 10 of the first embodiment in the following respects:

• a single capacitor 50' rather than capacitors 50(ChargeGate) and 50(DischargeGate);

• capacitor 50' is always connected to gate node 20;

• the NegativeFlush voltage need not have a large absolute value, but can be ground (or

^V GATEOFF); ^and

• no counterparts to blocks 70(precharge +) and 70(precharge -).

[0079] Thus, circuit 10' uses a single capacitor 50' (value C _CG ) to rapidly charge and discharge the gate. The capacitor is connected to gate node 20, and then is selectively charged by connection of the non-gate side of the capacitor to respective positive and negative voltage supplies 55P and 55N. In the specific embodiment, supply 55P provides a voltage that is significantly higher in absolute value than other characteristic voltages in the system, and supply 55N is ground or VQ _ATE O _FF . This is accomplished by a number of controlled switch blocks, each of which is shown schematically as including a control block and a switch. A reference to a block being turned on or off should normally be interpreted to mean that the switch within that block is being turned on or off.

[0080] In the first embodiment, the voltages provided by voltage supplies 55P and 55N were referred to as PositiveFlush (or V++) and NegativeFlush, respectively, with both

PositiveFlush and NegativeFlush being higher in absolute value than the maximum voltage that the gate can withstand. In this embodiment, voltage supply 55P provides a voltage, referred to as V+, that is typically higher in absolute value than the maximum voltage that the gate can withstand. Voltage supply 55N provides a voltage, designated V-, that is ground or VG _ATE O _FF (if a negative bias supply is used).

[0081] Again, as in the case of the first embodiment, the value of capacitor 50' is chosen so that the total charge on the capacitor when charged to V+ is within the levels that the device can tolerate. The particular voltage value (V+) and capacitor value (C _QQ ) are chosen in view of the packaging and interconnect, and the absolute voltage value for V+ can vary, say between several 10's of volts to more than 1000V. For example, if the circuit must be mounted far from the actual device, this may require a very small capacitor with a very high voltage to overcome the extra inductance of the long connection path but not overshoot the target value for the gate voltage. Circuit 10' includes a level translation circuit 60', which operates in essentially the same manner as level translation circuit 60 in the first embodiment.

[0082] A switch block 80'(ChargeGate), when turned on, connects capacitor 50' to supply 55P, which charges the capacitor and hence the gate. As will be described below, capacitor

50', while charged to the high voltage on supply 55P (e.g., +100V), does not expose the gate to this voltage; to do so would cause punch-through. Rather, the capacitor is sufficiently small so that the amount of charge, when transferred to the gate, charges the gate to a voltage that is sufficient for a full turn-on (say a voltage on the order of V _cc ). Similarly, a switch block 80'(DischargeGate), when turned on, connects capacitor 50' to supply 55N, which discharges the capacitor and hence the gate. By changing the voltage applied to the non-gate side of capacitor 50' (value C _CG ) by δV, the circuit transfers a charge of C _CG *(δV) to or from the gate node.

[0083] A switch block 90'(HoldGateOn), when turned on, provides a low-impedance path between gate node 20 and V _cc . Similarly, a switch block 90'(HoldGateOff), when turned on, provides a low-impedance path between gate node 20 and ground (or V _GATEOFF ). These switch blocks ensure stable levels on the gate between transitions, although this might be unnecessary in some situations where the gate, once charged or discharged, remains in that state in the absence of intervention. Thus these switch blocks should be considered preferred rather than necessary.

Second Embodiment — State Changes

[0084] FIG. 6A and FIG. 6B provide a state transition diagram of circuit 10' and device 25. The reasons for the state transitions in response to specific triggering events will not be described at this point, but will become clear in view of a later description of the circuitry in a particular embodiment. FIG. 6A shows the states and state transitions while FIG. 6B shows schematically the states of the switching blocks in each state. In an initial state 100' before power is applied to the system, there is no charge on any of the capacitors and device 25 is off. All the switch blocks are off and there is no charge on capacitor 50' (this state is not shown in FIG. 6B).

[0085] When power is turned on, the system transitions to a state 110' where the voltage supplies reach their designated voltages (V _cc , V+, V-, and V _GATEOFF ). In this state, switch blocks 90'(HoldGateOff) and 80'(DischargeGate) are on (switches closed) so that the gate is held off and capacitor 50' is discharged. Switch blocks 90'(HoldGateOn) and 80(ChargeGate) are off (switches open).

[0086] When Logic ln goes low, which means that D is low and D/ is high, this causes a transition to a state 120' where switch blocks 80'(DischargeGate) and 90'(HoldGateOff) are

turned on. Turning on switch block 8O'(DischargeGate) prevents the charging of capacitor 50'; turning on switch block 90'(HoldGateOff) holds the gate at ground and keeps the device off. As noted above, this may have been the condition before Logic_In went low, but state 120' is also entered during operation, and turning these two blocks on is necessary.

[0087] The overall control of the system delays the engagement of switch blocks

80'(ChargeGate) or 80'(DischargeGate) until the opposing switch blocks have both opened. Likewise the system delays the engagement of switch blocks 90'(HoldGateOn) or 90'(HoldGateOff) until semiconductor device 25 has changed states.

[0088] When Logic ln goes high, the system transitions to a state 130' where switch blocks 80'(DischargeGate) and 90'(HoldGateOff) are turned off, decoupling the gate and the capacitor from ground. This transition then turns switch block 80'(ChargeGate) on. The initially high voltage at gate node 20 overcomes the complex impedances between the gate node and the gate proper. This allows a high current charge transfer from capacitor 50' to the gate. At some point during the charge transfer of capacitor 50' in state 130, the voltage on the gate is sufficiently charged to turn device 25 on.

[0089] The change in the voltage on capacitor 50' causes a transition to a state 140' where switch block 90'(HoldGateOn) turns on, which provides a low impedance path between the gate and V _cc to keep the gate charged and keep the device in the fully on state.

[0090] When Logic ln goes low, the system transitions to a state 150' where switch blocks 90'(HoldGateOn) and 80'(ChargeGate) are turned off, thereby stopping the charging of capacitor 50' and decoupling the gate from V _cc . Thereafter switch block 80'(DischargeGate) is turned on. This allows a high current charge transfer from the gate to capacitor 50'.

[0091] A delayed response to Logic ln going low, timed to allow completion of the transfer of the gate charge to capacitor 50', causes the circuit to transition back to state 120', which was also entered in response to the initial Logic ln going low after power on.

[0092] It is noted that states 110', 120', 130', 140', and 150' are circuit states, which are different from the device ON and OFF states. In many instances, such as the description above, the context dictates whether a state that is referred to is a circuit state or a device state. In other contexts, it may be convenient to precede the mention of a state with the adjective "device" or "circuit" depending on the nature of the state being referred to.

Second Embodiment — Circuit Details and Operation

[0093] FIG. 7A and FIG. 7B are circuit schematics showing a specific implementation of gate drive circuit 10' as shown in FIG. 5, with FIG. 7A showing the portions of the gate drive circuit that are responsible for rapidly charging (turning on) and rapidly discharging (turning off) the gate, and FIG. 7B showing the portions of the gate drive circuit that are responsible for holding the gate on after the gate has been charged and holding the gate off after the gate has been discharged.

[0094] More specifically, FIG. 7A shows level translation circuit 60', switch block 8O'(ChargeGate), and switch block 80'(DischargeGate), while FIG. 7B shows switch block 90'(HoldGateOn) and switch block 90'(HoldGateOff).

[0095] A transistor Q3 in switch block 80(ChargeGate) transfers a quantity of charge to gate node 20 and ultimately to the gate proper. On completion of this transfer, switch block 90(HoldGateOn) is engaged through a high-speed isolator U4. A pair of transistors Q9 and QlO in switch block 90(HoldGateOn), PMOS transistors in this specific embodiment, provide the low impedance connection to the gate holding voltage once the charge on capacitor 50' has been transferred to the gate.

[0096] Switch block 80'(ChargeGate) is used to charge capacitor 50'. This occurs while the gate of the driven device's inductance fields form. A pair of transistors Q9 and QlO in switch block 90'(HoldGateOn), PMOS transistors in this specific embodiment, provide the low impedance connection to the gate holding voltage once capacitor 50' has been charged forming a charge divider between capacitor 50' and the gate of device 25. Fast control of the bilateral switch is effected using a high-performance gate drive chip U$9 with an isolated supply voltage (DCl) and isolated from other control components with a high speed digital isolator U4.

[0097] Switch block 90(HoldGateOff) provides a low impedance path to the gate turn off voltage source. It is delayed by the system control so as to allow switch block 80(DischargeGate) to complete the transfer of charge and turn off of the device under control of the circuit. Then, transistors Ql 2 and Ql 3, NMOS transistors in this specific embodiment, are turned on. Fast control of the bilateral switch is effected using a high-performance gate drive chip U$10 with an isolated supply voltage (DC2) and isolated from other control components with a high speed digital isolator U2.

[0098] Switch block 8O'(DischargeGate) is the control for the discharging of capacitor 50' used to turn off the device under control of the circuit. When the control signal goes low, transistor Q4 is turned on causing capacitor 50' to remove a charge of C _CG *(δV) from the gate. Switch block 80(DischargeGate) is the control for the transfer of charge in capacitor 50' through Q4 and subsequent engagement of 90'(HoId Gate Off) through U2.

[0099] FIG. 8 is a simplified timing diagram showing various voltages in the system. The bottom portion shows the differential signal (D, D/) derived from the input signal at Logic_In input 15. The upper portion shows the voltage on capacitor 50', which is substantially communicated to the gate node. As noted above, when power is turned on, the voltage supplies reach their designated voltages ( V _cc , V+, V-, and V _GATEOFF ), the device and the blocks remain off, and capacitor 50' is not charged. However, Logic ln is low, which means that D is low and D/ is high. This initiates discharging of capacitor 50' and the gate being pulled down to the negative bias voltage V _QATE O _FF , if present, or the gate being held at ground.

[0100] The transition of D going high initiates a rapid transfer of charge from capacitor 50' to the gate. The next transition of D going low initiates a rapid transfer of charge from the gate to capacitor 50'.

Second Embodiment — Determining the Gate Drive Parameters [0101] Once the characteristics of the switched semiconductor device are known, it is relatively straightforward to determine the value for capacitor 50', and the value for V+. The analysis is similar to that for the first embodiment.

[0102] Gated devices (FETs and IGBTs) are often described as voltage controlled but are actually charge controlled. The conductance of the device is more a function of the total charge on the gate, which is different from the voltage. As is well known, for linear devices such as capacitors, the capacitance, charge, and voltage are related by the equation V = Q / C (or equivalently, C = Q / V) where V is the voltage in volts, Q is the charge in coulombs, and C is the capacitance in farads. For gated devices, while the gate operates to store charge, it generally cannot be represented as a simple capacitor. Rather, complex impedances cause significant non-linearities in the voltage as a function of charge.

[0103] The actual maximum rate of change of charge on the gate of a device is not really known, as the best method of charging a gate to date has been to provide a very low

impedance path to a voltage source at the desired final gate voltage. Some device designs have used a negative bias supply to help remove the tails of the turn off current but that still uses a DC voltage applied to the gate. For any given device there is a maximum gate current that the device can tolerate and a maximum voltage between the gate and the source that the device can tolerate without breaking down.

[0104] As mentioned above, relevant device characteristics include:

• the full enhancement voltage;

• the full enhancement charge;

• the gate punch-through voltage; • the maximum current that can be allowed to flow into or out of the gate; and

• the gate impedance.

Of these quantities, the maximum current is not normally specified by the device manufacturer, but can be determined by testing the device

[0105] The analysis for charging the gate from capacitor 50' will be discussed. As mentioned above, in turning the device on, the gate will be driven to voltage V _cc , which is slightly (say a volt or two) above the full enhancement voltage but below the punch-through voltage. The desired value of charge on the gate will be referred to as Q _Q ATE-

[0106] Prior to transferring charge to the gate, the total charge on capacitor 50' is zero. The capacitor will be charged to V+ transferring C _QQ *((V+) - V _cc ) to the gate. The gate ends up at V _cc through the bilateral holding switch defined by transistors Q9 and QlO.

[0107] Therefore, a reasonable approximation is as follows:

CCG* V+ - QGATE (4)

Setting this constraint provides a safety margin and simplifies the calculation. More important to the user is the inductance between capacitor 50' and the actual gate. This inductance will cause an additional amount of charge to be transferred to the gate. However the now lower voltage at the gate node 20 provides negative feedback to quickly quench the current spike in the actual device gate while block 90 transitions to the ON state.

[0108] This sets a constraint on C _QQ and V+, but does not uniquely determine them. However, since it is desired to charge the gate as quickly as possible, V+ is preferably chosen

so that the initial current INITIAL * ^S below the device's maximum tolerable gate current value with appropriate device tolerance margin. If the system level gate impedance is Z,

Substituting this into Equation 4 and rearranging leads to:

C _CG = QGATE / ( ¹ INITIAL* ² ) (6)

[0109] Consider the following possible example for a given device:

Note that V _cc and QGATE ^{are n} °t/»er se specified device characteristics, but rather are values that are based on the full enhancement voltage and the full enhancement charge. For example, the design choice of 12 volts for V _cc might be based on a specified full enhancement voltage of 10 volts, i.e., 20% higher. While the gate is not a linear capacitor during the time it is being charged, it is a reasonable to assume a value for QGATE ^mat is also higher than the full enhancement charge. Similarly, I _γ NITIAL * ^S chosen to be lower than the tested maximum current for the device.

[0110] Substituting the "device-dependent" values of IγNITIAL ^an d Z into Equation 5 leads to a value for V+ of (250 amps)*(l ohm) = 250 volts. Substituting this value, along with the "device-dependent" values of QGATE ^an & Vco into Equation 6 leads to a value for C _CG of (2600 nanocoulombs) / (250 volts), or 10.4 nanofarads.

[0111] It should be recognized that the above calculations (and the ones for the first embodiment) provide values that may need to be varied for various design constraints. For example, while the computed value of 10.4 nanofarads for capacitors 50(ChargeGate) and 50(DischargeGate) in the first embodiment, and capacitor 50' in the second embodiment, components with precisely those values may not be readily available. AU values are not available for real components (e.g., small-value high-voltage capacitors may be available only for 10 nanofarads, and with tolerances of ±2% at best). Further, for design efficiency,

some users may decide to use voltage supply 45 (V _L OAD) ^t0 define V+ and then specify a capacitor that provides an appropriate safety margin. This may well result in the rapid charging putting the gate at a value that differs slightly from the holding voltage, in which case the holding switch would drain some charge off the gate or supplying the last bit of charge to the gate to move the device well in to the fully enhanced operating region.

Conclusion

[0112] In conclusion, it can be seen that the present invention provides simple but powerful techniques for improving the speed at which gated devices can be switched.

[0113] While the above is a complete description of specific embodiments of the invention, the above description should not be taken as limiting the scope of the invention as defined by the claims.