METHOD AND APPARATUS FOR DIRECT DIGITAL TO RADIO FREQUENCY

CONVERSION

Field of the Invention

[0001] The present invention relates generally to telecommunication and power amplification. The invention relates, more particularly, to conversion of digital data to high power RF signals and to power amplification systems suitable for use in high efficiency RF equipment.

Background

[0002] The development of highly efficient radio transmitters has been an objective of engineers since the 1930's. Recent developments in digital signal processing hardware have made possible the generation of multi-gigabit-per-second serial data streams. Such high speed data streams have been investigated for use as the driving waveform in high efficiency transmitters, in particular those employing switch mode Radio Frequency (RF) power amplifiers. An extension of this concept is the development of a transmitter which efficiently converts digital information directly to a radio frequency signal. Thus, there has been a push not only for highly efficient transmitters, but also for the ability to transition directly from a digital signal to a radio frequency signal.

[0003] An example of a Direct Digital to RF (hereinafter "DDRF") transmitter is shown in Figure 1. In such systems, I and Q information is converted through a digital signal processor (DSP) 102 into a format that is acceptable by a delta-sigma modulator 104. The delta-sigma modulator 104, usually a band-pass delta-sigma modulator, is used to create a binary drive waveform 106 (as shown by the binary output 106a, two-state, serial representation) which has desirable noise properties, such as a noise notch, in the vicinity of the carrier frequency as shown in the Delta- Sigma Output Spectrum 106b. This waveform is coupled to an efficient power

amplifier configured in a basic H-Bridge 126 format as is used in digital audio or motor controller applications. The two-state drive causes current to flow in alternating directions through the load 128 presented to the H-Bridge Power Amplifier, thus developing an amplified version of the desired RF output 130.

[0004] The operation of the H-bridge Power Amplifier 126 proceeds as follows: The binary output 106a of the Delta-Sigma Modulator determines which Field Effect transistors (hereinafter "FETs") are turned on or off. The binary signal is applied to the inputs of two inverting and two non-inverting driver stages. The driver outputs determine the gate-source voltage applied to each of the FETs, and are so configured as to permit only one diagonally opposite pair of FETs to be turned on at any given time. As an example, if a plus-one is transmitted to the H-bridge Power Amplifier 126, the FETi 132 and the FET ₄ 136 are turned on. As a result, current flows from FETi 132 through the load 128 to FET ₄ 136. When a minus-one (-1) is transmitted to the H-bridge Power Amplifier 126, the FET ₂ 134 and the FET3 138 are turned on. This causes current to flow from FET ₂ 134 through the load 128 to FET3 138. As can be seen, the current through the load 128 changes direction as the different pairs of FETs, 132 and 136 or 134 and 138, are turned on and off. This operation provides an alternating current to the load and delivers power to the load.

[0005] The signaling scheme described is a "+1" "-1" waveform. The rapid rise and fall times of such "square-edged" waveforms allow operation of the Power Amplifier (hereinafter "PA") devices (bipolar or FET) as idealized switches. Such an operation minimizes the power dissipation within the PA devices, leading to significant drain (or collector) efficiency improvement over that attained using traditional "sinusoidal" driving functions. The bandwidth of the "+1" "-1" waveform greatly exceeds that of the desired transmission channel bandwidth, extending from DC to at least 4 times the carrier frequency. Because of this bandwidth, a suitable band-pass filter is placed at the PA output to reject the unwanted off-channel energy and prevent such components from contributing to the "DC input" power required by the PA. In this regard, the H-bridge 126 has the unique property of being able to

accept a broadband drive signal yet discriminate against the DC input components corresponding to those spectral components which exist outside of the desired channel bandwidth. This acceptance of a broadband signal and discrimination of the DC input components is accomplished by the four device PA topology in conjunction with band pass filtering placed in series with the load. The DC component dissipated by the PA is restricted to that necessary to support the portion of the spectrum which is associated with the on-channel signal.

[0006] The binary output 106a of delta-sigma modulator is an undesirable driving waveform for RF applications. The two signal states represented by the plus- one (+1) minus-one (-1) waveform transfers a constant level of drive power to the PA, regardless of the signal amplitude delivered to the load 128. As many modulation systems such as CDMA and OFDM statistically spend much time at low power levels, the constant drive of the binary waveform implies the stage gain of the power amplifier will be low. In turn, the low gain requires significant drive power to be applied to the PA, resulting in low efficiency operation of the overall system. The need is therefore established for a direct digital to RF transmitter wherein the gain of the PA is maintained at a high level to promote high efficiency operation.

Brief Description of the Figures

[0007] The accompanying Figures, where like reference numerals refer to identical or functionally similar elements throughout the separate views and which together with the detailed description below, are incorporated in and form part of the specification, serve to further illustrate various embodiments and to explain various principles and advantages all in accordance with the present invention.

[0008] FIG. 1 is a prior art digital to radio frequency transmitter system incorporating a band-pass Delta-Sigma Converter and a basic H-bridge Power Amplifier.

[0009] FIG. 2A is an exemplary digital to radio frequency transmitter system with a multi-level delta- sigma modulator, a level select logic mapper and a 3 -level H- bridge.

[00010] FIGS. 2B-2E are exemplary representations of the operation of the 3- level H-bridge.

[00011] FIG. 3 is an exemplary digital to radio frequency transmitter system with a multi-level delta-sigma modulator, level select logic mapper and 4-level H- bridge.

[00012] FIG. 4A is an exemplary digital to radio frequency transmitter system with a multi-level delta-sigma modulator, level select logic mapper and 5 -level H- bridge.

[00013] FIGS. 4B and 4C are an exemplary digital to radio frequency transmitter systems utilizing half-bridge topology.

[00014] FIG. 5 is a representation of the increase in algorithmic efficiency achieved by various embodiments of the present invention.

[00015] FIG. 6. is an exemplary configuration for a multi-level H-bridge Power

Amplifier.

[00016] FIGS. 7, 8A, and 8B are exemplary diagrams of a configuration of the multi-level H-bridge.

[00017] FIGS. 9A and 9B are exemplary graphs of the Gate-Source drive voltage necessary to prevent drain-source inversion.

[00018] FIG. 10 is a prior art diagram of a configuration of the H-bridge Power

Amplifier with a Bootstrap Capacitor incorporated.

[00019] FIG. 11 is an exemplary configuration of a positive-negative floating drive source connected to the multi-level H-bridge.

[00020] FIG. 12 is an exemplary configuration of a multi-level H-bridge Power

Amplifier using six (6) devices.

[00021] FIG. 13 is an exemplary configuration of a positive-negative floating drive source connected to the 6-device multi-level H-bridge.

[00022] Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.

Detailed Description

[00023] Before describing in detail various embodiments in accordance with the present invention, it should be observed that the embodiments reside primarily in combinations of method steps and apparatus components related to Direct Digital to Radio Frequency ("DDRF") conversion and transmission. Accordingly, the apparatus components and method steps have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments of the present invention so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.

[00024] In this document, relational terms such as first and second, top and bottom, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such

relationship or order between such entities or actions. The terms "comprises," "comprising," "includes," "including," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises ...a" does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[00025] It will be appreciated that embodiments of the invention described herein may be comprised of one or more conventional processors and unique stored program instructions that control the one or more processors to implement, in conjunction with certain non-processor circuits, some, most, or all of the functions of Direct Digital to RF conversion described herein. The non-processor circuits may include, but are not limited to, a radio receiver, a radio transmitter, signal drivers, clock circuits, power source circuits, and user input devices. As such, these functions may be interpreted as steps of a method to perform direct digital to RF conversion. Alternatively, some or all functions could be implemented by a state machine that has no stored program instructions, or in one or more application specific integrated circuits (ASICs), in which each function or some combinations of certain of the functions are implemented as custom logic. Of course, a combination of the two approaches could be used. Thus, methods and means for these functions have been described herein. Further, it is expected that one of ordinary skill, notwithstanding possibly significant effort and many design choices motivated by, for example, available time, current technology, and economic considerations, when guided by the concepts and principles disclosed herein will be readily capable of generating such software instructions and programs and ICs with minimal experimentation.

[00026] Methods for receiving a digital signal, converting it to a radio frequency signal and amplifying it for transmission are disclosed. Various methods include receiving a digital signal, creating a modulated signal therefrom, and

amplifying the modulated signal with an H-bridge Power Amplifier. The various methods further include the transmitting of an amplified modulated signal.

[00027] Systems for receiving a digital signal, converting it to a radio frequency signal and amplifying the radio frequency signal for transmission are also disclosed. The systems may include a device for receiving a digital signal; a device for converting the signal into a modulated signal, and a device for amplifying the signal. The systems further include a transmitter for transmitting the amplified signal.

[00028] Referring now to Figure 1 , a prior art digital to radio frequency transmitter system incorporating a band-pass Delta-Sigma Converter and an H-bridge Power Amplifier is depicted. The digital to radio frequency system 100 includes an input for a modulated carrier 102 coming from standard digital processing (not shown). The modulated carrier is passed through a Delta-Sigma Converter 104. The Delta-Sigma Converter 104 can be a band-pass Delta-Sigma Converter. The Delta- Sigma Converter 104 outputs a binary drive waveform 106 that has a plus-one (+1) and minus-one (-1) amplitude. The binary drive waveform 106 has a time domain Binary output 106a and a corresponding Frequency Domain output 106b. The binary drive waveform 106 is input into an H-bridge amplifier 126.

[00029] The H-bridge amplifier 126 typically includes four drivers connected to FET devices. As the binary output 106a of the Delta-Sigma Modulator 104 is input into the H-bridge Power Amplifier 126, the various devices, bipolar or FET, are directed by the binary output 106a to turn off and on. As an example, if a plus-one (+l)is transmitted to the H-bridge Power Amplifier 126, the FETi 132 and the FET ₄ 136 are turned on. As a result, current flows from FETi 132 through the load 28 to FET ₄ 136. When a minus-one (-1) is transmitted to the H-bridge Power Amplifier 126, the FET ₂ 134 and the FET ₃ 138 are turned on. The turning from "off to "on" OfFET ₂ 134 and FET ₃ 138 causes current to flow from FET ₂ 134 through the load 128 to FET ₃ 138. As can be seen, the current through the load 128 changes direction as the different pairs of FETs, 132 and 136, or 134 and 138 are turned on and off. This

operation provides an alternating current to the load and delivers power to the load 128.

[00030] The H-bridge 126 has the unique property of being able to accept a broadband signal as its input, while restricting DC input power to only that which is necessary to support a desired narrowband output. This unique property is accomplished by use of the four-device H-Bridge PA topology in conjunction with band pass filtering placed in series with the load 128. The band pass filter rejects unwanted off-channel energy and prevents such frequency components from contributing to the DC input power required by the PA.

[00031] Since only a small fraction of the total broadband signal applied to the

PA falls within the desired pass-band around the carrier, the effective gain of the prior art H-bridge PA stage is low. While the drain (or collector) efficiency of the H- Bridge PA 126 may be acceptable, the overall system 100 efficiency expressed as Power-Added Efficiency ("PAE") is poor, due to the low gain of the PA stage (see equation 1).

p _AE __ PO(^UG ₁ DC input

[00032] In equation 1 , where PO is Power Output, Power Added Efficiency is seen to depend on the gain G of the H-bridge 126 amplifier stage as well the conversion efficiency of DC to RF power. For large values of G, PAE numerically approaches the value obtained for drain (or collector) efficiency formed by the ratio:

PO T Il ^d r ^a m = DC _l Tip _U t

Through extensive simulation and derivation efforts, insight into the operation of the delta-sigma converter 104 has been advanced. This is provided by equation 2 in the expression:

PAR _mput + |CJ = PAR _0Utput + tø J ^(eqn - ²⁾

P AR _input refers to the peak-to-average ratio of the signal applied to the input of the delta- sigma converter 104. Since this is a representation (digital or analog) of the desired on-channel signal, PAR _input is identical to analog PAR associated with the signal's modulation. C _BO represents the coding back-off required to maintain numeric stability of the feedback loop used by the delta- sigma converter 104 to provide the noise notch around the carrier. This quantity is a negative dB value of which the absolute value is taken for use in the equation. PAR _0Ut put is the peak-to-average ratio of the binary drive waveform 106 produced at the output of the delta-sigma converter 104, also expressed in dB. Finally, the quantity η _ALG is termed algorithmic efficiency and is defined as:

„ _ I LJ ON -CHANNEL _ ± LJ 'OONN-CHANNEL

^{LLG ~} PO _ON - _CHANNEL ⁺ P O o _FF - _CHANNEL ^~ TotalPowerGenerated

[00033] Algorithmic efficiency provides a figure of merit relating the ability of the delta-sigma converter 104 to produce the desired signal while generating minimal off-channel spectral components. ηAL _ϋ is represented as a negative dB value. Its absolute value is used in equation 2.

[00034] The significance of equation 2 will be illustrated using numerical values for the four quantities defined above. In the case of a CDMA carrier which is converted to a binary signaling representation, typical values are PAR _input = 6.OdB and C _BO ⁼ -1.9dB. Since the binary drive waveform 106 output of the delta-sigma converter 104 is a constant envelope signal, PARo _Ut put = OdB. Solving for the algorithmic efficiency term, |ηALG| has the value 7.9dB. ηALG subtracts directly from the gain which the H-bridge PA 126 would normally exhibit under narrowband, analog conditions. Thus, an H-bridge PA 126 exhibiting 1OdB of narrowband gain operates at a reduced gain of 2.IdB gain (10 - 7.9 = 2.IdB) resulting from the process of converting CDMA to a binary format.

[00035] Binary signaling can only produce two non-zero states (e.g. a plus-one and a minus-one signal), implying the total power generated (PO _O N _C HANNEL + PO _O FF _CHANNEL ) must remain constant. To create the desired on-channel CDMA signal, which has a time varying envelope, binary signaling must transfer power between on- channel and off-channel spectral components. This is accomplished by modulating the edge positions of the binary waveform as it transitions between the two states (which is essentially the only degree of freedom available). While the constant total power generated (PO _O N _C HANNEL + PO _O FF _C HANNEL) is applied to the H-bridge PA 126 input, only PO _O N _C HANNEL is delivered to the load 128. The gain of the H-bridge PA 126 stage is therefore reduced by the algorithmic efficiency as calculated above.

[00036] In contrast, a conventional analog representation of CDMA does not involve conversion to binary signaling. In equation 2, the absence of a delta-sigma converter 104 implies C _BO ⁼ OdB. Since all power generated in an analog system is on-channel power, ηALG = OdB. Thus, PAR _0Ut put= PAR _input since they are one in the same quantity. The hypothetical stage gain of 1OdB is preserved in an analog system. The analog representation of CDMA must be amplified to a practical output level in an analog linear amplifier, however. Such amplifier designs operate at low efficiency levels which are substantially poorer than those of switch-mode power amplifiers.

[00037] Revisiting equation 2, a technique for improving the algorithmic efficiency is necessary if a high efficiency digital transmitter is to be realized. The equation indicates this may be accomplished by increasing PAR _OU TP _U T for a given PAR _INPUT and C _BO - This presents a dilemma in that the switch-mode PA accepts only constant envelope, e.g., the plus-one (+1) minus-one (-1) discussed hereinabove. Application of non-constant envelope drive would force the switch-mode PA to spend time in the active region, where internal dissipation increases, resulting in poor efficiency.

[00038] Referring now to Figure 2A, an exemplary DDRF system 200 is shown.

The DDRF system 200 includes an input for a modulated carrier 102. The DDRF

system 200 further includes a Delta-Sigma Converter 202. The Delta-Sigma Converter 202 incorporates a quantizer 204 which produces a ternary output 206, e.g., three output states, plus-one (+1), zero (0) and minus-one (-1). The ternary output 206 drives a level select logic mapper 208. The level select logic mapper (hereinafter "mapper") 208 is a high speed device comprising digital logic and analog circuitry which interprets the output of the Delta-Sigma converter 202 into the appropriate gate drive signals for FETs of an H-Bridge PA 210., e.g. decoding of a multi-level serial signal into several single-level signals using a high speed ASIC or MMIC. The DDRF system 200 can have a frequency range of 20 MHz to 10 GHz at the output of the H-bridge PA 210.

[00039] The H-bridge PA 210 has four FETs, FET Qi 220, FET Q ₂ 222, FET

Q ₃ 224, and FET Q ₄ 226. The FET's Qi 220 and Q ₂ 222 are each connected at the drain node to a positive "A" voltage 228. The source node 230 of FET Qi 220 is connected to the drain node of FET Q ₃ 224. The source node of FET Q ₂ 222 is connected to the drain node of FET Q ₄ 226. A load 234 is connected on one side through a capacitance and an inductance to the source node 230 of FET Qi 220. The load 234 is connected on the other side through a capacitance and an inductance to the source node 232 of FET Q ₂ 222. The source node of FET Q ₃ 224 and FET Q ₄ 226 are connected to a negative voltage "A-" 236 potential

[00040] The mapper 208 is positioned between the multi-level delta-sigma converter 202 and the H-bridge PA 210. The mapper 208 is connected to the H-bridge PA 210 by four output connectors wherein, Vi 212 of the mapper 208 is connected to Vi 238 of FET Qi 220, V ₂ 214 of the mapper 208 is connected to V ₂ 240 of FET Q ₂ 222, V ₃ 216 of the mapper 208 is connected to V ₃ 242 of FET Q ₃ 224, and V ₄ 218 of the mapper 208 is connected to V ₄ 244 of FET Q ₄ 226.

[00041] The function of the mapper 208 is to determine which combinations of

FET devices 220, 222, 224, 226, of the H-Bridge PA 210 are driven to create each of the three states of the ternary output 206. Referring now to Figures 2B-2E, the plus-

one (+1) state occurs when Qi 220 and Q ₄ 226 are switched on, while Q ₂ 222 and Q3 224 are off. Current flows through the load 234 from left to right for the plus-one (+1) state. Conversely, the minus-one (-1) state is created when Q ₂ 222 and Q3 224 are switched on, while Qi 220 and Q ₄ 226 are off. The minus-one (-1) state allows current to flow from right to left through the load 234. A third or "zero" (0) state is realized in either of two ways: either Q3 224 and Q ₄ 226 are switched on while Qi 220 and Q ₂ 222 are off, or Qi 220 and Q ₂ 222 may be switched on, while Q3 224 and Q ₄ 226 are off. The zero (0) states facilitate the generation of the time-varying envelope of the desired signal by providing a "resting state" during which neither on-channel nor off-channel power is produced. Because of this, the ratio of on-channel power to total power generated (i.e.: the algorithmic efficiency) is increased. Table 1.1 illustrates the three states and the alternate state that are mapped by the mapper 208.

Table 1.1

[00042] For three level or ternary signaling, typical parameter values used in equation 2 are: PAR _input = 6.OdB, C _BO = -O.ldB, and PARoutput = 4.4dB, which result in ηAL _G = -1.7dB. Assuming the same 1OdB gain used in the binary signaling case, ternary signaling is seen to provide a much-improved H-bridge PA 210 stage gain of 8.3dB (10-1.7=8.3dB).

[00043] The reduction of C _BO is a secondary benefit provided by the introduction of the zero state in ternary signaling. As evident in equation 2, the reduction of CB _O acts together with the increase in PARoutputto improve |TIAL _G |- Note in Figure 2 that PARoutput = 4.4dB applied to the input of the four H-bridge PA 210

results in the desired 6.OdB PAR at the load 234, which is after the signal is efficiently amplified and passed through the output band-pass filter.

[00044] The zero (0) state cannot be created simply by removing the drive to the four FETs, Qi 220, Q ₂ 222, Q ₃ 224, and Q ₄ 226 of the H-bridge PA 210. Energy stored in the reactive elements of the output band-pass filter must be allowed to "ring out" through the load 234 to avoid device destruction and/or distortion of the desired on-channel signal. To accomplish this, either Q ₃ 224 and Q ₄ 226 or Qi 220 and Q ₂ 222 of H-bridge PA 210 must remain conducting ("ON") during the zero (0) state. Referring back to Figure 1, diodes D1-D4 may be provided to enable a path back to the power supply for switching transients which would otherwise attempt to force current in the reverse direction through a device when the device is turned off. Since the forward drops across the diodes need to be at least as small as the saturation voltage (e.g.: Vds) of the devices to effectively remove all stored energy, and the diodes themselves introduce non-linearities into the operation of the H-bridge PA 126, the use of "active commutation" wherein either Qi 220 and Q ₂ 222, or Q ₃ 224 and Q ₄ 226 are turned on is preferred.

[00045] Multiple-level signaling may be extended beyond ternary signaling to four levels. Referring now to Figure 3, an exemplary DDRF system 300 with a four- level delta-sigma modulator 302, four state level select logic mapper 304 and 4-level H-bridge 308 is shown. The DDRF system 300 can have a frequency range of 20 MHz to 10 GHz at the output of the H-bridge PA 308. Here the delta-sigma converter 302 receives a modulated carrier signal 102 and uses a four level quantizer 310 which produces a four - level output 312 and drives a four- state mapper 304.

[00046] The four level H-bridge 308 requires eight devices, Qi 314, Q ₂ 316, Q ₃

318, Q ₄ 320, Q ₅ 322, Q ₆ 324, Q ₇ 326, and Q ₈ 328 to provide four non-zero states of the four level signal 312. The four-level H-bridge 308 is described in further detail herein below. The four state mapper 304 is connected from eight outputs V ₁ -V ₈ to the

inputs Vi through V ₈ of the devices Qi 314, Q ₂ 316, Q ₃ 318, Q ₄ 320, Q ₅ 322, Q ₆ 324, Q ₇ 326, and Q ₈ 328 respectively.

[00047] The states, defined as plus-one-minus-one (±1) and plus-three-minus- three (±3), correspond to the voltage levels provided by two fixed power supplies ± Al and ± A2. The voltage levels are exemplary and could essentially be any voltage level as long as supply voltage Al, which corresponds to the |±1| voltage level, is less than supply voltage A2, which corresponds to the |±3| voltage level. As illustrated by table 1.2, note that an explicit zero state is not required in four-level signaling since one of the two H-Bridges comprising PA 308, e.g., the inner configuration of FETs Qi 314, Q ₂ 316, Q ₃ 318, and Q ₄ 320, or the outer configuration of FETs Q ₅ 322, Q ₆ 324, Q ₇ 326, and Q ₈ 328, is always conducting. A path is thereby provided to allow energy stored in the output filter to be delivered to the load 330.

Table 1.2

[00048] With regard to equation 2, typical CDMA values for four-level signaling are: PAR _input = 6.OdB, C _BO ⁼ -0.IdB, and PARo _Ut put = 5.5dB, which result in ηAL _G ⁼ -0.6dB. The resulting four level H-bridge PA 308 stage gain corresponding to the 1OdB reference value used previously is 9.4dB (10 - 0.6 = 9.4dB) for four-level signaling.

[00049] Five level signaling may be realized through the addition of a zero (0) state 410 to four-level signaling 412. Referring now to Figure 4 A, an exemplary

DDRF system 400 with a five-level delta-sigma modulator 402, a five state level select logic mapper 404a and 5-level H-bridge 408 is shown. Here the delta-sigma converter 402 receives a modulated carrier signal 102 and uses a five level quantizer 414 which produces a five - level output 412 and drives a five-state mapper 404a.

[00050] The five level H-bridge 408 requires eight devices, Qi 416, Q ₂ 418, Q ₃

420, Q ₄ 422, Q ₅ 424, Q ₆ 426, Q ₇ 428, and Q ₈ 430 to provide the five output states corresponding to the five level signal 412. The five -level H-bridge 408 can be the same as the four level H-bridge 308, which is described in further detail herein below. The five state mapper 404a is connected from eight outputs V ₁ -V ₈ to the inputs Vi through V ₈ of the devices Qi 416, Q ₂ 418, Q ₃ 420, Q ₄ 422, Q ₅ 424, Q ₆ 426, Q ₇ 428, and Q ₈ 430 respectively.

[00051] The states, defined as plus-one-minus-one (±1) and plus-two-minus- two (±2), correspond to voltage levels provided by two fixed power supplies ± Al and ± A2. The voltage levels are exemplary and could essentially be any voltage level as long as the supply voltage Al, which corresponds to the |±1| voltage level, is less than the supply voltage A2, which corresponds to the |±2| voltage level. As illustrated by table 1.3, either the lower pair of devices, Q ₇ 428 and Q ₈ 430, or the upper pair of devices, Q ₅ 424 and Q ₆ 426, associated with the higher voltage power supply is turned on during the zero state to provide the path by which energy stored in the output filter is delivered to the load 432. Alternatively, Q ₃ 420 and Q ₄ 422, or Qi 416 and Q ₂ 418, associated with the lower supply, may be turned on during the zero state if desired.

Table 1.3

[00052] For equation 2, typical CDMA values for five-level signaling are:

PAR _inpu ,= 6.OdB, C _BO = -0.05dB, and = 5.8dB, resulting in ηAL _G = -0.25dB. For the reference gain of 1OdB used previously, four level signaling results in a PA stage gain of 9.75dB.

[00053] Improved algorithmic efficiency and stage gain occur with increasingly complex (more levels) signaling. Figure 5 illustrates the results of multiple simulations for which an algorithmic efficiency 502 vs. number of signaling levels 504 plot was obtained. While diminishing returns 506 appear to be reached after seven to eight (7-8) signaling levels 506, practical systems are likely to be limited to three to five (3-5) levels because of the increased hardware complexity associated with additional levels. Stated another way, the improvement of η _ALG is very large when comparing an exemplary 2-level H-Bridge configuration to a 5 -level H-Bridge configuration. But, as the number of levels increases above five (5) levels, the improvement per additional level moves towards an asymptote at 0 dB 507. Note however, that additional signaling levels may be introduced simply by selecting the appropriate pairs of H-Bridge switches within topologies such as Figure 3. For example, an intermediate level may be created by closing switches Q6 324 and Q3 318 or Q5 322 and Q4 320.

[00054] In practice, the actual ηAL _G achieved for a given number of signaling levels will be somewhat degraded from the values shown in Figure 5. This is due to the non-ideal behavior of the band-pass filter placed at the PA output, and sinc-roll- off associated with the sample-and-hold operation that must be performed on the waveform driving the PA. However, it should be noted that while previous artisans have sought to make the analog systems more like digital systems, the ηAL _G achieved

for a given number of signaling levels illustrates that the converse is true such that a digital system should be made to look like an analog system instead.

[00055] The embodiments have been discussed in the context of improved power added efficiency (PAE); however multiple level signaling is seen to produce an improvement in drain efficiency as well. If the switching devices used in the H- Bridge were ideal, all on-channel power would pass through the output filter to the load, while off-channel power would be completely rejected by the filter. None of the off-channel signal components would contribute to the DC input power consumed by the H-Bridge. The actual switching FETs that may be used in the H-Bridge have a small but finite capacitance between the drain and source. This capacitance creates a "leakage path" by which off-channel signal components are shunted around the output filter, resulting in increased DC input power and lower drain efficiency. The improved algorithmic efficiency associated with multiple level signaling concentrates more energy in the on-channel spectrum, reducing the amount of off-channel signal available for the leakage path. As an example, for an H-bridge constructed from practical device technologies and in accordance with the embodiments, an improvement in drain efficiency of about 10% can be realized with three-level signaling over that of two-level signaling. Further efficiency improvements may be achieved through the use of a switching device technology that minimizes the drain- source capacitance. Semiconductor technologies having a high power density, such as Gallium Nitride may be used.

[00056] An exemplary symmetric H-Bridge topology, commonly known as a

"full-bridge," has been illustrated. Those skilled in the art will recognize that a half- bridge topology as shown in Figure 4B may be used as well. The exemplary half bridge topology may be implemented by using only the left side, Qi 416, Q ₃ 420, Q ₅ 424, and Q ₇ 428, of the H-Bridge 458. The right side of the load 432 is connected to ground at node 434. The mapper 404b provides only 4 outputs: V ₁ , V ₃ , V5 and V ₇ . This latter topology uses four FETs and is capable of four-level operation.

[00057] Referring now to Figure 4C, another embodiment of a half-bridge implementation is illustrated. The half-bridge 478 utilizes three (3) devices instead of the four shown in the half-bridge 458 of Figure 4B. The device Qs 424 is eliminated. Q ₇ 428 is connected at one 480 to a ground. The right side of the load 432 connected to ground at node 434. The mapper 404c provides only 3 outputs: V ₁ , V ₃ , and V ₇ . Additionally, the Delta-Sigma Converter 202 with quantizer 204 may be used. This latter topology uses three FETs and is capable of three-level operation. The disclosure of these alternate power amplifier topologies in no way detracts from or supersedes the pervading principles described herein.

The Multi-Level H-Bridge

[00058] Referring now to Figure 6, an exemplary configuration for a multilevel H-bridge Power Amplifier is shown. The multiple-level H-bridge Power Amplifier (hereinafter "H-bridge") 600 is comprised of eight bipolar or FET devices, an outside top left FET _OTL 602, an inside top left FETπx 604, an inside top right FETi _TR 606, and outside top right FET _OTR 608, an outside bottom left FET _OBL 610, an inside bottom left FET _IBL 612, an inside bottom right FET _IBR 614, and an outside bottom right FET _OBR 616. These devices can be Gallium Nitride FETs, Gallium Arsenide, or other transistors of comparable or greater switching frequency capability. A positive potential of +3 volts 618 is connected to the drain node of FET _OTL 602. The source node of FET _OTL 602 is connected to node V _s di 620. A positive potential of +5 volts 622 is connected to the drain node of FETπχ604. The source node of FET _γγL 604 is connected to node V _s di 620. The drain node of FET _OBL 610 is connected to node Vsdi 620 as well as the drain node of FET _IBL 612. The source node of FET _OBL 610 is connected to the negative potential -3 Volts 624 while the source node of FET _IBL 612 is connected to the negative potential -5 Volts 626. A positive potential of +5 volts 628 is connected to the drain node of FETi _TR 606. The source node of FETiTR 606 is connected to node V _s dr 630. A positive potential of +3 volts 632 is connected to the drain node of FET ₀ TR 608. The source node of FET _OTR 608 is connected to node V _s d _r 630. The drain node of FETQ _BR 616 is connected to node V _s dr

630 as well as the drain node of FET _IBR 614. The source node of FET _OBR 616 is connected to the negative potential -3 Volts 634 while the source node of FET _IBR 614 is connected to the negative potential -5 Volts 636. A load 638 is connected between the left configuration 642 the right configuration 640 of the multi-level H-bridge 600. One end of the load 638 is connected through a capacitor 644 and an inductor 646 to Vsdi 620. The other end of the load 638 is connected through capacitor 648 and inductor 650 to V _s d _r 630. Artisans of ordinary skill will appreciate that the use of the three (3) volt and five (5) volt supplies is for illustrative purposes and in no way limits the scope of the invention.

[00059] Referring now to Figure 7, an exemplary left side configuration 640 of the multi-level H-bridge 600 is shown. To turn on any of the devices will require a gate-source voltage of six (6) volts for FET _OTL 602 and FET _OBL 610 and a gate-source voltage often (10) volts for FETi _TL 604, andFET _ffiL 612. The left configuration 640 will never have more than one device turned on at one time. Artisans of ordinary skill will appreciate that the left configuration 640 is illustrated for exemplary purposes. The right configuration 642 will be configured in a mirrored manner as shown in Figure 6. Therefore, only one device on each side of the multi-level H-bridge 600 will be turned on at one time (e.g. for a total of two devices over the multi-level H- bridge 600). To turn off any of the devices, the gate-source voltage will equal zero (0) volts. As an example, to turn off FET _OBL 610, V _OBL 702 must equal negative three (-3) volts to make the gate-source voltage V _gs =0 volts. Furthermore, the drain-source voltage Vds can be assumed to be 0 volts at saturation for any of these devices; this assumes that the devices operate as perfect switches. Depending upon the particular application and semiconductor device technology employed, the gate-source voltages required to turn a particular device on or off may differ from the values illustrated. Further, the full gate-source potentials (six volts for FET _OTL 602 and FET _OBL 610 and ten volts for FET _ITL 604, andFETi _BL 612) may be larger than the minimum potential necessary to rapidly turn-on a particular FET. This is dependant upon which FET had been turned on immediately prior in time. Since the drive power required by a FET increases with the applied gate-source voltage swing, it may be advantageous to scale

the gate-source potentials in response to the specific time sequencing of the various FETs shown in Figure 7. The scaling of the gate-source potentials may be done under circumstances where drive power consumption must be limited. For ease of illustration however, a voltage equal to the full supply potential (six volts or ten volts) will be assumed as the gate-source voltage necessary to turn a particular FET on, as stated above.

[00060] Referring now to Figure 8A, an exemplary left side configuration 640 of the multi-level H-bridge 600 is shown. A ten (10) volt potential is applied to V _ITL of FETiTL 604 such that the Gate- Source Voltage, V _gs = Vi _TL - V _sd i= 10 volts. Therefore, FET _ITL 604 is turned to the "ON" state. FET _ITL 604 saturates when it is in the "ON" state. The saturation of FET _ITL 604causes the voltage drop from its drain to the source to become zero (0) volts. V _sd i 620 thus becomes five (5) volts. Recall that FET ₀ TL 602 is off for V _O TL - V _sd i=0 volts. Since V _sd i 620 is five (5) volts and V _O TL - V _s di=0 volts, V _OTL now becomes five (5) volts. Note that V _s di 620 equaling five (5) volts causes a drain-source reversal at FET _OTL 602, due to the fact that FETs are symmetrical devices. The voltage V _OTL -3 represents a positive gate-source voltage Vgs for the reversed FET _OTL 602 with respect to the +3 volt supply. As a result, FET _OTL 602 conducts current 802 into the +3 volt supply. However, if V _OTL - V _s di=-2 volts, then the gate-source V _gs (V _O TL-3) becomes zero (0) volts and FET _O TL 602 remains "OFF". This situation only occurs when the device next to FET _OTL 602 is turned on, e.g., when FET _n - _L 604 is turned "ON."

[00061] Referring now to Figure 8B, an exemplary left configuration 640 of the multi-level H-bridge 600 is shown. FET _IBL 612 saturates when it is in the "ON" state The saturation of FET _IBL 612 causes the voltage drop from the drain to the source to become zero (0) volts. As a result, V _sd i 620 becomes negative five (-5) volts. Recalling that FET ₀ BL 610 is "OFF" when its V _gs =0 volts, thus V _OBL -(-3) = 0 volts, and V _OBL = -3 volts. Again, a drain source reversal occurs due to the fact that the FET is a symmetrical device. At FET _OBL 610, V _OBL - V _s di becomes a positive V _gs . As a result, FET _0BL 610 conducts current 804 from the negative three (-3) volt supply into

the negative five (-5) volt supply. However, if V _OBL is set to negative five (-5) volts, then V _O BL-(-3) = -2 volts. Thus, V _O BL - V _s di becomes zero (0) volts and FET _O BL 610 does not turn on. To ensure the outer FET devices remain in the off state, a gate source voltage of -2 volts must be applied whenever the nearby inner device is turned on. Using the previous example, Figure 9A depicts a method wherein a voltage of -2 volts is applied across V _gs of FET _OBL 610 only when the nearby device, FET _IBL 612, is turned on. Because the input power required to drive the switching device is the product of the gate current and gate-source voltage swing, the part-time usage of -2 volts for Vgs, reduces the average power needed to drive the switch. The same approach may be applied to the upper FET switches, FET _OTL 602 and FETi _TL 604. Alternatively, the Vgs waveform shown in Figure 9B may be used, however, the larger voltage swing increases the required drive power, effectively reducing the gain ofthe H bridge PA 600.

[00062] Referring now to Figure 10, a prior art diagram of a configuration of the H-bridge Power Amplifier with a Bootstrap Capacitor incorporated is shown. An upper FET device 1002 and a lower FET device 1004 of one side of an H-bridge are shown. The lower FET device 1004 is connected on the source node to a voltage source A- 1006. The lower FET device 1004 is further connected to at the drain node to a central node 1008. Additionally, the lower FET has the gate node connected to a lower driver 1010. The upper FET 1002 is connected at the drain node to a voltage source A+ 1012, the source node connected to the central node 1008, and the gate node connected to an upper driver 1014. A load 1016 is connected at one end to the central node 1008. A capacitor Cl 1018 is connected at the bottom node to the central node 1008 and at the top node to a diode Dl 1020. The diode Dl 1020 is further connected to the voltage source A+ 1012. The upper driver 1014 is additionally connected at one input to the top node of the capacitor Cl 1018 and at another input to the central node 1008. (These "inputs" of driver 1014 are its A+ and A- terminals.)

[00063] When the lower FET device 1004 connected to voltage source A- 1006 is turned on, the capacitor Cl 1018 charges. The capacitor Cl 1018 builds a charge from A+ 1012 through the diode Dl 1020. The charge is used to operate the upper driver 1014 which, in turn, is used to drive the upper device 1002. The circuit configuration accommodates the time varying voltage present at central node 1008, which is connected to the load 1016 and is varying up and down in voltage potential from A+ to A- as the upper device 1002 and lower device 1004 are turned on and off. The lower device 1004 is referenced to A- 1006 while the upper device 1002 is referenced to the central node 1008 which, as previously stated, will vary up and down. The upper driver 1014 needs to be able to follow the reference on the source of the upper device 1002 and be able to control the voltage on the gate of the upper device 1002 regardless of the voltage present on the central node 1008. Because the bottom of the capacitor Cl 1018 and the bottom of the upper driver 1014 are connected to the central node 1008, the upper driver 1014 can track the voltage on the central node 1008 as the central node's voltage varies. Thus, the upper driver 1014 can add the appropriate potential to the time-varying voltage present at the central node 1008.

[00064] Referring now to Figure 11 , an exemplary configuration of a positive- negative drive source connected to the multi-level H-bridge is shown. A floating drive source 1102 is connected between the level select logic mapper 1104 and a multi-level H-bridge 1106. For illustration purposes, only one half of the multi-level H-bridge 1106 is shown. However, one of ordinary skill in the art would appreciate that an identical configuration exists for the other half of the multi-level H-bridge 1106. The mapper 1104 can be like the previous mapper's 208, 304, 404 described hereinabove. The mapper 1104 can be one mapper 1104 that drives both halves of the multi-level H-bridge 1106, or it can be two mappers 1104 wherein one mapper 1104 drives one half of the multi-level H-bridge 1106 and the other mapper 1104 drives the other half of the multi-level H-bridge 1106.

[00065] The floating drive source 1102 is comprised of a top 3-level driver

1108, a top 2-level driver 1110, a bottom 3-level driver 1112, and a bottom 2-level driver 1114. Each of the drivers 1108, 1110, 1112, 1114 are connected to the level select logic mapper 1104. Additionally, each of the drivers 1108, 1110, 1112, 1114 are connected to a top node 1116 of a capacitor Cl 1118. Capacitor Cl 1118 is connected to a central node 1120. A diode Dl 1122 is connected at its cathode to the top node 1116 of capacitor Cl 1118. The diode Dl 1122 is connected at its anode to a top switch 1124. The top switch 1124 is further connected to a top voltage source 1126 of +8 volts. A top regulator 1128 is connected across capacitor Cl 1118 by connecting to the top node 1116 of capacitor Cl 1118 and to the central node 1120. The top regulator 1128 controls the top switch 1124 to charge the capacitor Cl 1118 capacitance to a minimum supply needed for the drivers 1108, 1110, 1112, 1114. The drivers 1108, 1110, 1112, 1114 are additionally connected to a bottom node 1128 of a second capacitor C2 1130. The capacitor C2 1130 is also connected to the central node 1120. A second diode D2 1132 is connected its anode to the bottom node 1128 of the capacitor C2 1130. The diode D2 1132 is connected at its cathode to a bottom switch 1134. The bottom switch 1134 is additionally connected to a bottom voltage source 1136 of negative-eight (-8) volts. A bottom regulator 1138 is connected across the capacitor C2 1130 by connecting to the bottom node 1128 of the capacitor C2 1130 and to the central node 1120. The bottom regulator 1138 controls the bottom switch 1134 to charge the capacitor C2 1130 capacitance to a minimum negative supply needed for the drivers 1108, 1110, 1112, 1114.

[00066] The multi-level H-bridge 1106 can be like the previous multi-level H- bridge's 308, 408, described hereinabove. A left configuration of the multi-level H- bridge 1106 is shown. The multi-level H-bridge 1106 comprises an outer top device 1140, an inner top device 1142, an outer bottom device 1144 and an inner bottom device 1146. The outer top device 1140 is connected at a drain node to a +3 voltage source 1148. The outer top device 1140 is additionally connected at a source node to the central node 1120. The inner top device 1142 is connected at a drain node to a +5 voltage source 1150 and connected at a source node to the central node 1120. The

outer bottom device 1144 is connected at a source node to a negative-three (-3) voltage source and connected at a drain node to the central node 1120. The inner bottom device 1146 is connected at a source node to a negative-five (-5) voltage source 1154 and connected at a drain node to the central node 1120. A load 1176 is also connected at one end to the central node 1120. The top 3-level driver 1108 is connected to the gate node of the outer top device 1140. The top 2-level driver 1110 is connected to the gate node of the inner top device 1142. The bottom 3-level driver 1112 is connected to the gate node of the outer bottom device 1144 and the bottom 2- level driver 1114 is connected to the gate node of the inner bottom device 1146.

[00067] The floating drive source 1102 is setup such that when either the outer bottom device 1144 or the inner bottom device 1146 is turned on, the capacitor Cl 1118 charges through the diode Dl 1122. Additionally, if either the outer top device 1140 or the inner top device 1142 is turned on, the capacitor C2 1130 charges through the diode D2 1132. The floating drivers 1108, 1110, 1112, 1114 are connected on a top supply side to capacitor Cl 1118 and on a bottom supply side to the capacitor C2 1130. Therefore, each of the floating drivers 1108, 1110, 1112, 1114 is provided a ± power supply potential referenced to central node 1120. As such, the 3-level top driver 1108, and the 3-level bottom driver 1112 are each adapted to create a V _gs voltage of positive 6 volts (+6V), 0 volts, and negative 2 volts (-2V) for the outer top device 1140 and the outer bottom device 1144. The 2-level top driver 1110 and the 2- level bottom driver 1114 each can create a V _gs voltage of either positive 10 volts (+10V) or 0 volts for the inner top device 1142 and the inner bottom device 1146.

[00068] The mapper 1104, which may be an ASIC in some embodiments, is adapted to receive the multi-level signal, e.g., four or five level signal 1156 and generate an appropriate drive signal for each of the floating drivers 1108, 1110, 1112, 1114. The mapper 1104 can set the 3-level top driver 1108 and the 3 level bottom driver 1112 to one of three states to generate an appropriate V _gs of negative -two (-2) volts, zero (0) volts or positive-six (+6) volts, based on the input signal. The mapper 1104 additionally sets the 2-level top driver 1110 and the 2-level bottom driver 1114

to one of two states to generate an appropriate V _gs of zero (0) volts or positive-ten (+10) volts based on the input signal 1156.

[00069] Referring now to Figure 12, an exemplary configuration of a multilevel H-bridge Power Amplifier using six devices is shown. The six device H-bridge 1202 is comprised of six devices, FET _0TL 1204, FETi _TL 1206, FET _n -R 1208, FET _O TR 1210, FETiBL 1212, andFET _ffi R 1214. The outer-top-left FET _0TL 1204 is connected at the drain node to a +6 volt supply 1216. FET _OTL 1204 is additionally connected at the source node to V _sd i 1218. The inner-top-left FETi _TL 1206 is connected at the drain node to a +10 volt supply 1220. FET _ITL 1206 is also connected at the source node to Vsdi 1218. The inner-bottom-left FET _IBL 1212 is connected at the drain node to V _s di 1218 as well. However, FET _IBL 1212 is connected at the source node to a ground 1222 as is the source node of FET _ffiR 1214. The drain node of FET _ffiR 1214 is connected to V _sdr 1224. Both FET _γγR 1208 and FET _OTR 1210 are connected at their source nodes to V _s dr 1224. FET _γTR 1208 is connected at the drain node to the +10 volt supply 1220 while FET _OTR 1210 is connected at the drain node to the +6 volt supply 1216. A load 1226 is connected between V _sd i 1218 and V _sdr 1224 as shown. The load 1226 may be connected through series filters 1228 and 1230.

[00070] Referring now to Figure 13, an exemplary configuration of a positive- negative floating drive source connected to the six-device multi-level H-bridge is shown. For illustration purposes, only the left half of the six device H-bridge 1202 is shown. However, one of ordinary skill in the art would appreciate that a mirrored configuration exists for the other half of the six device H-bridge 1202. A floating drive source 1302 for a six device H-bridge 1202 is connected between a mapper 1304 and the six device H-bridge 1202. The mapper 1304 can be like the previous mapper's 208, 304, 404 1104 described hereinabove. The mapper 1304 can be one mapper 1304 that drives both halves of the six device H-bridge 1202, or it can be two mappers 1304 wherein one mapper 1304 drives one half of the six device H-bridge 1202 and the other mapper 1304 drives the other half of the six device H-bridge 1202. The floating drive source 1302 has a 3-level top driver 1306, a 2-level top driver 1308,

and a 2-level bottom driver 1310. A capacitor Cl 1312 is connected on the top node to the cathode of a diode Dl 1314 as well as to the top of each of the drivers 1306, 1308, 1310. The capacitor Cl 1312 is connected on the bottom node to V _s di 1218. The anode of the diode Dl 1314 is connected through a top switch 1316 to a positive- sixteen (+16) volt supply 1318. A bottom node of a capacitor C2 1320 is connected an anode of a diode D2 1322 as well as to the bottom of each of the floating drivers 1306, 1308, 1310. The top node of capacitor C2 1320 is connected to V _sd i 1218. The diode D2 1322 is additionally connected through a bottom switch 1324 to a negative- sixteen (-16) volt supply 1326. Additionally, a top regulator 1328 controls the switch 1316 to charge the capacitor Cl 1312 capacitance to a minimum supply needed for the drivers 1306, 1308, 1310. A bottom regulator 1330 controls the bottom switch 1324 to the capacitor Cl 1320 capacitance to the minimum negative supply needed for the drivers 1306, 1308, 1310.

[00071] Whenever FET _ffiL 1212 is turned on, capacitor Cl 1312 charges through the diode Dl 1314. Additionally, whenever either FET _OTL 1204 or FET _ITL 1206 is turned on, the capacitor C2 1320 charges through diode D2 1324. The 3-level top driver 1306 is connected to the gate node of FET _OTL 1204. The 2-level top driver 1308 is connected to the gate node of FET _ITL 1206. The 2-level bottom driver 1310 is connected to the gate node of FET _IBL 1212. Therefore, since the capacitor Cl 1312 is connected to the tops of each of the floating drivers 1306, 1308, 1310 and capacitor C2 1320 is connected to the bottom of each of the floating drivers 1306, 1308, 1310, each of the floating drivers is provided with a ± power supply referenced to central node 1218 to drive the devices FET _O TL 1204, FETITL 1206, and FET _ffiL 1212. The 3- level top driver 1306 is adapted to create a V _gs voltage of negative-four (-4) volts, zero (0) volts and positive-six (+6) volts for FET _OTL 1204. The 2-level top driver 1308 creates a V _gs voltage of zero (0) volts or positive-ten (+10) volts for FET _ITL 1206 and the 2-level bottom driver 1310 creates a V _gs voltage of zero (0) volts or positive- ten (+10) volts for FETIBL 1212.

[00072] The mapper 1304 is adapted to receive the multi-level signal, e.g., a three, four or five level signal 1156 and generate a drive signal to each of the floating drivers 1306, 1308, and 1310. The mapper 1304 can set the 3-level top driver 1306 to one of three states to generate an appropriate V _gs of negative-four (-4) volts, zero (0) volts or positive-six (+6) volts, based on the input signal. The mapper 1304 additionally sets the 2-level top driver 1308 and the 2-level bottom driver 1310 to one of two states to generate an appropriate V _gs at, zero (0) volts or positive-ten (+10) volts based on the input signal.

[00073] In the foregoing specification, specific embodiments of the present invention have been described. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention. The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. The invention is defined solely by the appended claims including any amendments made during the pendency of this application and all equivalents of those claims as issued.