Field of Invention

The present invention relates generally to a method for packing semiconductor components or devices. More specifically, the present invention relates to a method for fabricating a flip-chip semiconductor package.

Background

Semiconductor packaging typically involves encapsulating or housing a semiconductor component or device, for example a semiconductor chip, within a device carrier or substrate. The device carrier or substrate supports the semiconductor chip and facilitates a convenient handling of the semiconductor chip. In addition, the device carrier comprises external connections or terminals for electrically connecting the semiconductor chip to an external circuit.

A known method of semiconductor packaging, more specifically a method of forming a flip-chip on leadframe (FCOL) semiconductor package, employs a plated leadframe. A leadframe is a patterned sheet of metal. The sheet of metal, which is typically copper, is commonly plated with one of silver, nickel or palladium. Plating is necessary to prevent the sheet of metal from oxidizing, and to provide a surface onto which solder will adhere or, when employing wire bonding, gold or aluminum can be bonded. The pattern of the sheet of metal provides a leadframe for forming the FCOL semiconductor package.

Typically, leadframes for forming FCOL semiconductor packages have leads with inner lead portions and outer lead portions. The inner lead portions are arranged in a pattern with interconnect locations on the inner lead portions matching pattern of pads formed on a surface of the semiconductor chip. Solder bumps or balls are deposited on the pads formed on the surface of the semiconductor chip. Reflow of the solder bumps facilitates bonding of the pads of the semiconductor chip with the leadframe, more specifically with the interconnect locations on the inner lead portions of the leadframe. The semiconductor chip is then placed on the leadframe with the pads of the semiconductor chip abutting the interconnect locations on the inner lead portions of the leadframe. Assembly of the semiconductor chip and the leadframe is then heated to an elevated temperature to reflow the solder bumps for forming solder interconnects between the semiconductor chip and the leadframe. The heating of the assembly is typically performed in a heating chamber or oven. The resultant semiconductor package formed is known in the art as the FCOL semiconductor package.

Current heating processes for reflowing the solder bumps as described above have been considered to be significantly time consuming, thereby impairing fabrication or manufacturing efficiency and throughput of semiconductor packages.

In addition, coefficient of thermal expansion (CTE) of the semiconductor chips generally differs from CTE of the leadframes or other substrates. Accordingly, differential expansion occurs between the semiconductor chip and the leadframe when the assembly of the semiconductor chip and the leadframe is heated. The differential expansion between the semiconductor chip and the leadframe can cause misalignments between the solder bumps on the pads of the semiconductor chips and the solder bumps on the inner lead portions of the leadframe, thereby resulting in impaired or malfunctioning solder interconnects between the semiconductor chip and the leadframe. Such mis-alignments and impaired solder interconnections are especially prevalent with semiconductor chips or packages having a fine pitch.

The increasing functionality, speed and portability of modern electronic devices have resulted in an increasing need for more electronic components or elements to be integrated into the semiconductor chip. Accordingly, reduction of the pitch or distance between adjacent pads or electrical interconnects, and between the solder bumps formed thereon, of the semiconductor chip is increasingly important in the semiconductor industry.

However, the reduced pitch or distance between pads or electrical interconnects of the semiconductor chip increases risk, and occurrences, of bridging between the adjacent pads or electrical interconnects, thereby resulting in electrical shorting. Correspondingly, the increased risk, and occurrences, of electrical shorting between adjacent pads or electrical interconnects adversely affects the reliability and quality of the fabricated semiconductor packages.

Accordingly, a person skilled in the art will appreciate that an improved method for fabricating flip-chip semiconductor packages capable of addressing at least one of the above-identified issues is needed.

Summary

The present invention provides an exemplary method for semiconductor component or device packaging for addressing at least one of the above-identified issues.

In accordance with a first aspect of the present invention, there is disclosed a method for device packaging, the method comprising heating a semiconductor device to a first temperature. The semiconductor device comprises a plurality of bump structures, each of the plurality of bump structures comprising a solder portion. The first temperature is at least the melting temperature of the solder portion of each of the plurality of bump structures. The method further comprises heating a substrate to a second temperature, the substrate comprising a plurality of contact pads and spatially aligning, through the use of an alignment means, the plurality of bump structures with the plurality of contact pads subsequent the heating of the semiconductor device and the substrate. The semiconductor device is disposed away from the substrate during heating of the semiconductor device to the first temperature and at least one of the semiconductor device and the substrate is subsequently displacable towards the other thereof for abutting each of the plurality of bump structures with a corresponding one of the plurality of contact pads.

In accordance with a second aspect of the present invention, there is disclosed a system for packaging a device, the system comprising means for heating a semiconductor device to a first temperature. The semiconductor device comprises a plurality of bump structures, each of the plurality of bump structures comprising a solder portion. The first temperature is at least a melting temperature of the solder portion of each of the plurality of bump structures. The system further comprises means for heating a substrate to a second temperature, the substrate having a plurality of contact pads. The system further comprises an alignment means for spatially aligning the plurality of bump structures with the plurality of contact pads subsequent the heating of the semiconductor device and the substrate. The semiconductor device is disposed away from the substrate during heating of the semiconductor device to the first temperature. Heating of the semiconductor device to the first temperature enables the solder portions to reach melting point for being at a molten phase. The at least one of the semiconductor device and the substrate is subsequently displaceable towards the other thereof for abutting each of the plurality of bump structures with a corresponding one of the plurality of contact pads. Thickness of at least one of the semiconductor device and the substrate is calibrated for controlling displacement of the at least one of the semiconductor device and the substrate towards the other thereof.

Brief Description of Drawings

Exemplary embodiments of the present invention are described hereinafter with reference to the following drawings, in which:

FIG. 1 is a partial method flow diagram of an exemplary method for fabricating a flip- chip semiconductor package according to an embodiment of the present invention;

FIG. 2 is a partial process flow diagram of an exemplary semiconductor chip processing process performed in a step of the exemplary method of FIG.1 ;

FIG. 3a to 3h illustrates the steps of the exemplary semiconductor chip processing process of FIG. 2:

FIG. 4. is a partial process flow diagram of an exemplary substrate processing process performed in a step of the exemplary method of FIG. 1 ;

FIG. 5a to 5i illustrates the steps of the exemplary substrate processing process of FIG. 4;

FIG. 6 is a partial process flow diagram of an exemplary flux transfer process performed by a step of the exemplary substrate processing process of FIG. 4; FIG. 7 illustrates the steps of the exemplary flux transfer process of FIG. 6;

FIG. 8 is a partial process flow diagram of an exemplary bonding process performed in a step of the exemplary method of FIG. 1,

FIG. 9a to FIG. 9d illustrates the steps of the exemplary bonding process of FIG. 6;

FIG. 10 shows a partial formula for managing displacement height during the exemplary bonding process of FIG. 6;

FIG. 1 1 shows a partial process flow diagram of key steps of the exemplary method of FIG. 1 ;

FIG. 12 shows an exemplary temperature profile during the exemplary method of FIG. 1 ;

FIG. 13 shows a partial cross-sectional view of the flip-chip semiconductor package fabricated by the exemplary method of FIG. 1 ;

FIG. 14 shows an exploded partial cross-sectional view "A" of the flip-chip semiconductor package of FIG. 13;

FIG. 15a to 15b provides a diagrammatic overview of pitch compensation between solder bumps or interconnects formed on the substrate of the flip-chip semiconductor package that is fabricated by the exemplary method of FIG. 1 ;

FIG. 16 shows a partial system diagram of an exemplary system for fabricating a flip- chip semiconductor package according to an embodiment of the present invention;

FIG. 17 and 18 show partial isometric views of exemplary bond stages of the exemplary system of FIG. 16; and

FIG. 19 shows a partial isometric view of the water cooling mechanism of the exemplary system of FIG. 16. Detailed Description

Existing methods for fabricating flip-chip semiconductor packages typically position solder bumps formed on pads or pillars of a semiconductor chip onto contact pads formed on a device carrier (for example a substrate) before heating the assembly of the semiconductor chip and device carrier to reflow the solder bumps and form solder interconnects between the semiconductor chip and the device carrier. This heating process is typically time-consuming, thereby adversely affecting fabrication or manufacturing efficiency and throughput of the flip-chip semiconductor packages. Existing methods also commonly involve use of considerable force for abutting the pads of the semiconductor chip with the contact pads of the device carrier in order to create a reliable solder joint. Accordingly, the considerable force used can result in damage to the semiconductor chip or device carrier during heating thereof. In addition, existing methods for fabricating flip-chip semiconductor packages have been associated with a problem of electrical shorting between adjacent interconnects formed between semiconductor chips and device carriers. This problem of electrical shorting between adjacent interconnects is especially prevalent with semiconductor chips and packages having a fine pitch. Furthermore, an accurate positioning or alignment of the semiconductor chip in relation to the device carrier during formation of interconnects or solder interconnects therebetween can also be difficult to achieve. Accordingly, the present invention provides an improved method for packaging semiconductor devices, more specifically an improved method for fabricating semiconductor flip-chip packages, which is capable of addressing at least one of the above-identified problems.

For purposes of brevity and clarity, the description of embodiments of the present invention provided hereinafter is limited to methods for fabricating or manufacturing a flip-chip semiconductor package. It will however be understood by a person skilled in the art that this does not preclude the present invention from other applications where fundamental principles prevalent among the various embodiments of the present invention such as operational, functional or performance characteristics are required. An exemplary method 100 for fabricating a flip-chip semiconductor package 10 is provided according to an embodiment of the present invention. A method flow diagram of the exemplary method 100 is shown in FIG. 1.

In a step 1 10 of the exemplary method 100, a semiconductor device or component is processed. The semiconductor device is for example, and will hereinafter be referred to as, a semiconductor chip 12.

Preferably, the processing of the semiconductor chip 12 occurs via performance of an exemplary semiconductor chip processing process 200 that is provided by the present invention. A process flow diagram of the exemplary semiconductor chip processing process 200 is shown in FIG. 2.

In a step 210 of the exemplary semiconductor chip processing process 200, the semiconductor chip 12 is provided. Preferably, the semiconductor chip 12 is provided on a chip tray 14 or chip container containing multiple semiconductor chips 12. The semiconductor chip 12 preferably comprises bump structures 16 formed on a surface thereof. Such bump structures 16 preferably comprises a metal post 18 with a solder portion 20 formed at a free end of the metal post 18. Solder type used for the solder portion 20 includes, but is not limited to, metals and metal alloys such as silver and tin.

Alternatively, the bump structures 16 are similar to that of pillar bumps as described in US patent application 09/564,382, which is incorporated in the present description by reference. Alternatively, the semiconductor chip 12 comprises bumps or solder bumps formed on contact pads (collectively referred to as a pad array) formed on the surface of the semiconductor chip 12. The bump structures 16 are for mediating electrical communication of the semiconductor chip 12 with a substrate 22 or external circuitry. It will be understood by a person skilled in the art that alternative bump structures or electrical interconnects can also be used for performing the above- identified function of the bump structures 16.

In a step 220, the semiconductor chip 12 is transferred from the chip tray 14 to a chip pickup tool 24. To perform the step 220, a transfer tool 26 or gripper is used to pick up the semiconductor chip 12 from the chip tray 14. Preferably, the transfer tool 26 applies vacuum or suction for picking up the semiconductor chip 12, and for securing the semiconductor chip 12 to the transfer tool 26. The transfer tool 26 then flips the semiconductor chip 12 180-degrees vertically to position the semiconductor chip 12 at a pickup position for subsequent pickup by, or transfer to, the chip pickup tool 24. It will however be understood by a person skilled in the art that the transfer tool 26 may be alternatively displaced or rotated for displacing and positioning the semiconductor chip 12.

A thickness or height of the semiconductor chip 12 is then measured in a step 230. Preferably, the semiconductor chip 12 is transferred to a height calibration stage (not shown) for measuring the thickness or height of the semiconductor chip 12. The thickness or height of the semiconductor chip 12 is measured using an encoder (not shown), which is coupled to the chip pickup tool 24 for determining spatial position thereof. Preferably, calibration of the chip pickup tool 24 is performed by first reading back an encoder value at a point of contact with a first vision lens 30, which serves as a datum plane, followed by measuring additional encoder values when in contact with a reference gauge positioned on the first vision lens 30.

The semiconductor chip 12 is also orientated or aligned in the step 230. More specifically, the semiconductor chip 12 is orientated or aligned for corresponding to a slot (not shown) formed on a chip preheat stage 28. The positioning or orientating of the semiconductor chip 12 is facilitated by use of the first vision lens 30. The first vision lens 30 enables vision correction or vision alignment of the semiconductor chip 12 before being positioned on the chip preheat stage 28.

In a subsequent step 240, the semiconductor chip 12 is placed on the chip preheat stage 28. More specifically, the semiconductor chip 12 is preferably placed on the slot formed on the chip preheat stage 28. The semiconductor chip 12 is preferably held or secured to the chip preheat stage 28 by vacuum or suction. Alternatively, the semiconductor chip 12 is held or secured to the chip preheat stage 28 by mechanical means, for example by a gripper (not shown). The semiconductor chip 12 placed on the chip preheat stage 28 is then preheated to a predetermined temperature in a step 250. The predetermined temperature is for example 200 ^° C. The preheating of the semiconductor chip 12 is performed gradually by displacing the semiconductor chip 12 across a series of heaters 34 towards a bond tool location. More specifically, the semiconductor chip 12 is attached to a preheat buffer stage, also known as a turret, which is rotated for displacing the semiconductor chip 12 across the series of heaters 34. The heaters 34 are preferably convection heaters. Temperature of each heater 34 is preferably preset to provide incremental heating of the semiconductor chip 12 as it progresses from one to another of the heaters 34 along the series. Heating of the semiconductor chip 12 by the heaters may be effected by at least one of conduction, convection or radiation. Further preferably, the temperature of each heater 34 can be kept constant or can be varied as required.

The gradual preheating of the semiconductor chip 12, which can also be referred to as controlled preheating, of the semiconductor chip 12 reduces or eliminates thermal shock to the semiconductor chip 12. It will be understood by a person skilled in the art that preheating profile of the semiconductor chip 12 can be adjusted as required by altering any one or more of the temperatures of the radiation heaters 34. It will also be understood by a person skilled in the art that preheating profile of the semiconductor chip 12 can be adjusted as required by altering speed of displacement of the preheat stage and/or spacing between the semiconductor chip 12 and the radiation heaters 34. Control of the speed of the chip preheat stage 28 and control of the preheating of the semiconductor chip 12 can be either manually or software controlled.

As previously mentioned, the chip preheat stage 28 is displaced towards the bond tool location during the step 250. At the bond tool location, the semiconductor chip 12 is picked up by a bond tool 36 in a step 260. The semiconductor chip 12 is preferably held or secured to the bond tool 36 by vacuum or suction. Alternatively, the semiconductor chip 12 is held or secured to the bond tool 36 by mechanical means, for example by a gripper (not shown).

Preferably, the bond tool 36 is preheated and maintained at a predetermined elevated temperature prior to pick up of the semiconductor chip 12 in the step 260. The predetermined temperature is preferably sufficiently high enough to melt the solder portions 20 of the bump structures 16. The predetermined elevated temperature of the bond tool 36 is for example 260°C. It will however be understood by a person skilled in the art that the predetermined elevated temperature can be adjusted as required by methods well-known in the art. It will also be understood that the temperature of the bond tool 36 can be adjusted, more specifically increased or decreased, as required after the semiconductor chip 12 is picked up thereby. Control of temperature of the bond tool 36 can be either manually or software controlled.

The semiconductor chip 12 is then heated by the bond tool 36 to a chip processing temperature in a step 270. During the heating of the semiconductor chip 12 to the chip processing temperature, the temperature of the bond tool 36 is preferably maintained at the predetermined temperature, for example at 260°C. Preferably, the chip processing temperature is sufficiently high for heating the semiconductor chip 12 to thereby melting the solder portions 20 of the bumps structures 16 formed on the semiconductor chip 12. In addition, the chip processing temperature is preferably sufficiently high enough for maintaining the solder portions 20 of the bump structures 16 at the molten or liquid phase. The temperature of the bond tool 36 can be varied as required after the semiconductor chip 12 is received thereby. The variation or alteration of the temperature of the bond tool 36 can be effected using methods known to a person skilled in the art.

In a step 280, the bond tool 36, with the semiconductor chip 12 attached thereto, is positioned above a second vision lens 38. The second vision lens 38 facilitates x, y translational and θ angular alignment of the semiconductor chip 12 relative to the substrate 22. More specifically, the second vision lens 38 facilitates x, y translational and θ angular alignment of the bump structures 16 of the semiconductor chips 12 relative to bond pads 64 or bump structures (also known as interconnects) formed on the substrate 22.

Completion of the step 280 preferably completes the semiconductor chip 12 processing process 200. It will however be understood by a person skilled in the art that other semiconductor chip 12 processing steps and techniques may be additionally performed by the process 200. The exemplary method 100 further comprises a step 120 of processing the substrate 22. The step 1 10 and the step 120 are preferably performed simultaneously. Alternatively, the step 1 10 and the step 120 are performed sequentially.

The substrate 22 may be a carrier, or a part of the carrier, for the semiconductor chip 12. Alternatively, the substrate 22 may be a leadframe. Preferably, the processing of the substrate 22 occurs via performance of an exemplary substrate processing process 300 provided by the present invention. A process flow diagram of the exemplary substrate processing process 300 is shown in FIG. 4.

In a step 310 of the exemplary substrate processing process 300, the substrate 22 is provided. Preferably, the substrate 22 is provided via a substrate magazine 50. The substrate 22 is then picked up by a substrate pickup tool 52 or device and transferred onto a flux stage 54 in a step 320. The substrate 22 is preferably held or secured to the flux stage 54 by vacuum or suction. Alternatively, the substrate 22 is held or secured to the flux stage 54 by mechanical means, for example by a gripper (not shown).

In a step 330, flux 56 (also known as fluxing agent) is transferred from a flux transfer stage 58 onto a surface of the substrate 22, more specifically onto the bond pads 64 of the substrate 22. The step 330 is preferably effected via an exemplary flux transfer process 400. A process flow diagram of the exemplary flux transfer process 400 is shown in FlG. 6.

In a step 410 of the exemplary flux transfer process 400, a predetermined quantity of flux 56 is dispensed on the flux transfer stage 58. The flux 56 or fluxing agent comprises of one or more materials or chemicals, which are known to a person skilled in the art. In a step 420, a tampon tool 60 is pressed onto the flux 56 on the flux transfer stage 58. Preferably, the tampon tool 60 is pressed onto the flux 56 with a predetermined pressure. A tip 62 of the tampon tool 60 is elastic and conforms to a pattern formed on the flux transfer stage 58. Preferably, the pattern formed on the flux transfer stage 58 corresponds to a pattern of holes or structures (not shown) formed on the flux transfer stage 58. Preferably, flux 56 is contained within the holes or structures formed on the flux transfer stage 58. The pattern of holes or structures formed on the flux transfer stage 58 can be determined and altered as required using techniques known to a person skilled in the art. Preferably, the pattern of holes or structures on the flux transfer stage 58 corresponds with pattern of bond pads 64 formed on the substrate 22. A portion of the flux 56 adheres to or is picked up by the tip 62 of the tampon tool 60 when it is pressed onto the flux 56 on the flux transfer stage 58. Preferably, the pattern of holes or structures on the flux transfer stage 58 is determined for localizing the flux 56 transferred from the flux transfer stage 58 onto the bond pads 64 of the substrate 22. In other words, the pattern of holes on the flux transfer stage 58 preferably enhances accuracy of flux transfer onto the bond pads 64 of the substrate 22.

In a subsequent step 430, the tampon tool 60 is aligned or positioned above the substrate 22. Preferably, the tampon tool 60 is aligned or positioned in relation to the bond pads 64 formed on the surface of the substrate 22. In a step 440, the tampon tool 60 is then displaced for pressing onto the surface of the substrate 22 at a predetermined speed and pressure.

Pressing of the tampon tool 60 onto the surface of the substrate 22 preferably causes a transfer of flux 56 from the tip 62 of the tampon tool 60 onto the surface of the substrate 22 in a step 450.

Although only the exemplary flux transfer process 400 is described above, a person skilled in the art will understand that other methods and apparatuses for transfer flux 56 onto the surface of the substrate 22 may be utilized for performing the step 330.

For example, the transfer of flux 56 in the step 330 may be effected by screen printing or pin transfer techniques or methods. Use of pin transfer preferably enables auto- alignment and provides a more robust flux-transfer process for parallelism/flatness because of the soft-pin design. Alternatively, the flux 56 may be directly dispensed onto the surface of the substrate 22.

It will also be understood by a person skilled in the art that the flux 56 may comprise any one or more of fluxing materials or agents commonly known to a person skilled in the art. The flux transfer process 400 can also be substituted with use of a no-flow underfill. The no-flow underfill can be transferred or dispensed onto the surface of the substrate 22 via methods known to a person skilled in the art. For example, the no-flow underfill may be directly dispensed onto the substrate 22 by use of a needle (not shown).

In a step 340, the substrate 22 comprising flux 56 on the surface thereof is transferred from the flux stage 54 onto a substrate preheat stage 66 (also known as a substrate preheat plate or holder) by a substrate pickup tool 72. Preferably, the substrate preheat stage 66 is preheated and maintained at a predetermined elevated temperature, for example 150 ^° C. It will be understood by a person skilled in the art that the predetermined elevated temperature of the substrate preheat stage 66 can be predetermined and varied as required using techniques known in the art.

In a step 350, the substrate 22 on the substrate preheat stage 66 is heated to a transition temperature. The transition temperature of the substrate 22 can be selected, and is further variable, as required. Control of heating of the substrate 22 on the substrate preheat stage 66 can be either manually or software controlled.

The transfer of flux 54 occurring in the step 330 may alternatively be performed after the substrate 22 has been transferred onto the substrate preheat stage 66 and heated to the transition temperature.

In a step 360, the substrate 22 is transferred from the substrate preheat stage 66 to a bond stage 70 (also known as a bond plate or holder) using a substrate transfer tool 72. The substrate pickup tools 52 and 68 and the substrate transfer tool 72 may be the same tool. The substrate 22 is preferably held or secured onto the bond stage 70 by use of a vacuum or suction. Alternatively, the substrate is held or secured onto the bond stage 70 by alternative mechanical means or mechanism. Preferably, the vacuum or suction is applied at specific or predetermined positions on the substrate 22 held onto the bond stage 70. More preferably, the specific positions do not correspond to bond pad 64 locations on the substrate 22. This is to prevent deformation or warping of the substrate 22 when the substrate 22 is heated. Preferably, the bond stage 70 is preheated and maintained at a predetermined elevated temperature. The predetermined elevated temperature of the bond stage 70 is for example 200°C. The predetermined elevated temperature of the bond stage 70 can be selected and varied as required using techniques known to a person skilled in the art. Temperature of the bond stage 70 can be either manually or software controlled.

The temperature of the bond stage 70 can be selected and varied depending on numerous factors. For example, the temperature of the bond stage 70 can be selected and varied depending on melting point of the solder portions 20 on the bump structures 16. Preferably, the temperature of the bond stage 70 is maintained at a temperature that is incapable of melting the solder portions 20 on the bump structures 16 of the semiconductor chip 12, and incapable of maintaining the solder portions 20 on the bump structures 16 of the semiconductor chip 12 at the molten or liquid phase. Further preferably, the temperature of the bond stage 70 is maintained at a temperature lower than the melting point of the solder portions 20 of the bump structures 16 of the semiconductor chip 12. The temperature of the bond stage 70 can further depend on activation temperature of the flux or on curing temperature of the no-flow underfill (when the no-flow underfill is used in place of the flux).

The temperature of the bond stage 70 can be varied as required after the bond stage 70 receives the substrate 22. The variation or alteration of the temperature of the bond stage 70 can be effected using methods known to a person skilled in the art. The bond stage 70 is designed for reducing or preventing heat dissipation from the substrate 22 to the bond stage 70. Preferably, the bond stage 70 is designed such that copper traces, which may be present on the substrate 22, do not come into contact with the bond stage 70 so as to minimize heat dissipation or heat losses. Alternatively, the bond stage 70 is designed such areas thereof in contact with the copper traces are constructed from heat insulating materials including, but not limited to, ceramic.

The substrate 22 positioned on the bond stage 70 is then further heated by bond stage 70 to a substrate processing temperature in a step 370. The substrate processing temperature of the substrate 22 is preferably lower than the chip processing temperature of the semiconductor chip 12. Alternatively, the substrate processing temperature of the substrate 22 is equal or similar to the chip processing temperature of the semiconductor chip 12. Preferably, the heating of the substrate 22 to the transition temperature in the step 350 reduces time required for the further heating of the substrate 22 to the substrate processing temperature in the step 370. The temperature of the bond stage 70 is preferably maintained at the predetermined elevated temperature, for example 200°C.

In a step 380, a thickness or height of the substrate 22 is measured and recorded by a substrate thickness measurement tool 74 or apparatus. The substrate thickness measurement tool 74 preferably determines the thickness or height of the substrate 22 with reference to a datum defined by the bond stage 70. Further preferably, the substrate thickness measurement tool 74 measures thickness of the substrate 22 excluding the bond pads 64 and flux 56. Preferably, the substrate thickness measurement tool 74 further measures at least one of thickness of flux 56 on the substrate 22 and height of bond pads 64, also known as contact pads, formed on the substrate 22.

The bond stage 70 is then positioned below the second vision lens 38 in a step 390. Preferably, the second vision lens 38 facilitates at least one of x, y translational and θ angular alignment of the substrate 22 relative to the semiconductor chip 12. More specifically, the second vision lens 38 facilitates x, y translational and θ angular alignment of the bond pads 64 formed on the substrate 22 relative to the bump structures 16 formed on the semiconductor chip 12. The second vision lens can alternatively be referred to as a look-up/look-down camera for facilitating at least one of x, y translational and θ angular alignment of the substrate 22 relative to the semiconductor chip 12. It will however be appreciated by a person skilled in the art that the x, y translational and θ angular alignment of the bond pads 64 formed on the substrate 22 relative to the bump structures 16 formed on the semiconductor chip 12 can be effected by a third vision lens (not shown) or other alignment means known in the art.

The processing of the semiconductor chip 12 in the step 1 10 and the processing of the substrate 22 in the step 120 prepares the semiconductor chip 12 and the substrate 22 for bonding therebetween in a step 130. Preferably, the bonding between the semiconductor chip 12 and the substrate 22 in the step 130 occurs via an exemplary bonding process 500 provided by the present invention. A process flow diagram of the exemplary bonding process 500 is shown in FIG. 8.

As previously described the second vision lens 38 facilitates at least one of x, y linear and θ angular alignment of the semiconductor chip 12 relative to the substrate bond pad locations. More specifically, the second vision lens 38 facilitates at least one of x, y linear and θ angular alignment of the bump structures 16 formed on the semiconductor chip 12 with the bond pads 64 formed on the substrate 22.

In a step 510, the bond tool 36 positions and aligns the semiconductor chip 12 above the substrate 22 positioned on the bond stage 70. Preferably, the positioning of the semiconductor chip 12 above the substrate 22 in the step 510 aligns the bump structures 16 of the semiconductor chip 12 with the bond pads 64 of the substrate 22.

Preferably, the second vision lens 38 facilitates a definition of a first coordinate system of the semiconductor chip 12 and a number of reference axes intersecting and configuratively corresponding with the bump structures 16 of the semiconductor chip 12. In addition, the second vision lens 38 further facilitates a definition of a second coordinate system of the substrate 22 and a number of reference vertices coinciding and configuratively corresponding with the bond pads 64 of the substrate 22. Preferably, the second vision lens 38 is coupled or electrically communicable with a programmable controller (not shown).

The programmable controller is preferably programmed for defining the first coordinate system and the second coordinate system. In addition, the programmable controller enables alignment of the first coordinate system with the second coordinate system for substantially coinciding each of the number of reference axes with a corresponding one of the number of reference vertices to thereby enable or aid a accurate spatial alignment of the bump structures 16 of the semiconductor chip 12 with the bond pads 64 of the substrate 22.

The semiconductor chip 12 is preferably at the chip processing temperature and the substrate 22 is preferably at the substrate processing temperature. The maintenance of the semiconductor chip 12 at the chip processing temperature preferably maintains the solder portions 20 on the bump structures 16 thereof at the molten or liquid phase.

In a step 520, a first phase movement or displacement of the bond tool 36 towards the bond stage 70 occurs. Movement of the bond tool 36 towards the bond stage 70 displaces the semiconductor chip 12 attached to the bond tool 36 towards the substrate 22 on the bond stage 70. The first phase movement of the bond tool 36 in the step 520 is preferably performed at a fast speed, which can be predetermined and is further alterable as required.

In a step 530, a second phase movement or displacement of the bond tool 36 further towards the bond stage 70 occurs. Movement of the bond tool 36 towards the bond stage 70 displaces the semiconductor chip 12 attached to the bond tool 36 towards the substrate 22 on the bond stage 70. The second phase movement of the bond tool 36 is preferably at a slower speed as compared to the first phase movement of the bond tool 36. The slower speed of the bond tool 36 during the second phase movement minimizes risk of molten or liquid solder wicking or splashing to adjacent bond pads 64 and causing unwanted electrical shorting.

The steps 520 and 530 facilitate a positioning of the semiconductor chip 12 and the substrate 22 at a bonding position in a step 540. It will be appreciated by a person skilled in the art having the disclosure provided by the present description that additional phases of movement or displacement of the bond tool 36 relative to the bond stage 70 may be effected. Movement of the bond tool 36 during such additional phases of movement may be of faster or slower speeds as compared to the speeds of either the first page movement in the step 520 or the second phase movement in the step 530. In addition, movement of the bond tool 36 during such additional phases of movement may be towards or away from the bond stage 70.

At the bonding position, the molten or liquid solder portions 20 of the semiconductor chip 12 contacts corresponding bond pads 64 of the substrate 22. The separation or spacing between the semiconductor chip 12 and the substrate 22 at the bonding position can be referred to as a bond distance (also known as a separation distance). Preferably, the bond distance is determined and is further variable as required based on the thickness of the substrate 22 as measured in the step 380. Further preferably, the bond distance is further determined or varied based on height of the semiconductor chip 12 measured in the step 230. The height of the semiconductor chip 12 is preferably taken to comprise height of the bump structures 16 formed thereon. An exemplary calculation formula for measuring and managing bond distance (and distances between the semiconductor chip 12 and the substrate 22 during the steps 520 to 540) is shown in FIG 10. It will be appreciated, that the magnitude of displacement of the bond tool 36 towards the bond stage 70 during the first phase and second phase movement of the steps 520 and 530 respectively is carefully determined and selected for positioning the bump structures 16 of the semiconductor chip 12 onto corresponding bond pads 64 of the substrate 22.

Height or thickness of semiconductor chip or die (Hd) is measured during the step 230. Height or thickness of the substrate (Hs) is measured during the step 380. Preferably, the magnitude of displacement of the semiconductor chip 12 during the steps 520 and 530 is known as actual stroke. The actual stroke is calculated using the exemplary calculation formula as shown in FIG. 10. Preferably, the actual stroke is calculated by subtracting Hd and Hs from a reference height (Hf), which is a height between the bond tool 36 and bond stage 70 or between the semiconductor chip 12 and the substrate 22, and adding a predetermined compression offset value (i.e. Actual Stroke = Hf - Hd - Hs + compression offset value). The compression offset is added for overcoming any co-planarity variances from the semiconductor chip 12 and the substrate 22. Management of the bond distance (and distances between the semiconductor chip 12 and the substrate 22 during the steps 520 to 540) enhances accuracy and stability of bonds formed between the semiconductor chip 12 and the substrate 22.

The bond tool 36 and the bond stage 70 respectively maintain the semiconductor chip 12 and the substrate 22 at the chip processing temperature and the substrate processing temperature respectively. Temperature of each of the bond tool 36 and the bond stage 70 is preferably carefully controlled and managed during the method 100. An exemplary temperature profile during the method 100 is shown in FIG. 12. Preferably, the temperature of each of the bond tool 36 and the bond stage 70 can be carefully and accurately measured, monitored and regulated as required during the method 100. Preferably, the control and maintenance of the temperatures of each of the bond tool 36 and the bond stage 70 correspondingly enables thermal management of the semiconductor chip 12 and the substrate 22 respectively during the bonding process 500. In addition, the control and maintenance of the temperatures of each of the bond tool 36 and the bond stage 70 helps control and maintain temperature at junctions between the solder portions 20 of the bump structures 16 and the bond pads 64.

As previously described, it is important to set and maintain the temperature of the bond tool 36 for heating the semiconductor chip 12 to a sufficiently high temperature for melting the solder portion on the bump structures 16 thereof, and to maintain the solder portions 20 of the bump structures 16 of the semiconductor chip 12 at the molten or liquid phase.

Preferably, the bond stage 70 is designed and structured for preventing fast heat drainage (i.e. for retaining heat there within). Preferably, the bond stage 70 comprises an insulating layer 76 coupled thereto or incorporated therewithin. The insulating layer 76 helps slow heat drainage or heat transfer through the bond stage 70. This is to say, the insulating layer 76 prolongs retention of heat within the bond stage 70. Preferably, heat retained within the bond stage 70 maintains the temperature at the junctions between the solder portions 20 of the bump structures 16 and the bond pads 64 of the substrate 22 at a sufficiently high temperature for maintaining the solder portions 20 at the molten or liquid state. The insulating layer 76 preferably comprises air pockets or air bubbles therewithin. Alternatively, the insulating layer 76 is made of a material having a low thermal conductivity.

Preferably, a water-cooled setup or mechanism 610 is coupled to the bond stage 70 for reducing or preventing heat dissipation from the bond stage 70 to the other components. The water-cooled setup or mechanism 610 preferably comprises at least one plate positioned adjacent a surface of the bond stage 70, and at least one pipe connector 612 for circulating fluid through the at least one plate to thereby reduce heat dissipation from (or insulated) the bond stage 70. In a step 550, the semiconductor chip 12 and the substrate 22 are maintained at the bonding position for a predetermined time period to thereby allow or facilitate sufficient bonding or interconnect formation between the semiconductor chip 12 and the substrate 22. More specifically, the semiconductor chip 12 and the substrate 22 are maintained at the bonding position for a predetermined time period to facilitate sufficient bonding between the solder portions 20 on the bump structures 16 of the semiconductor chip 12 and the bond pads 64 of the substrate 22.

Preferably, the semiconductor chip 12 and the substrate 22 are brought to a bonding temperature during the step 550. More specifically, junctions between the bump structures 16 of the semiconductor chip 12 and the bond pads 64 of the substrate 22 are brought to the bonding temperature during the step 550. The bonding temperature during the step 550 is preferably between the chip process temperature and the substrate process temperature. More specifically, the bonding temperature is lower than the chip process temperature and higher then the substrate process temperature.

The bond tool 36 then releases the semiconductor chip 12 onto the substrate 22 in a step 560. Preferably an air purge by the bond tool 36 occurs before the release of the semiconductor chip 12 onto the substrate 22 in the step 560. The air purge facilitates removal or detachment of the semiconductor chip 12 from the bond tool 36. Preferably, pressure of the air purge is controlled for preventing application of unwanted pressure onto the molten solder present between the semiconductor chip 12 and the substrate 22, more specifically between the bump structures 16 of the semiconductor chip 12 and the bond pads 64 of the substrate 22. The solder between the bump structures 16 on the semiconductor chip 12 and the bond pads 64 of the substrate 22 then solidifies for completing the bonding between the semiconductor chip 12 and the substrate 22.

Performance of the steps 110 to 130 of the exemplary method 100 facilitates bonding of the semiconductor chip 12 to the substrate 22 for forming the flip-chip semiconductor package 10. A partial cross-sectional view of the flip-chip semiconductor package 10 is shown in FlG. 13 and FIG 14. This is also to say that the steps 1 10 to 130 of the exemplary method 100 represent steps in a method for packaging the semiconductor chip 12. In a step 140, the formed flip-chip semiconductor package 10, more specifically assembly of semiconductor chip 12 bonded with the substrate 22, is transferred or offloaded from the heated bond stage 70 to an offload stage (not shown). The flip- chip semiconductor package 10 then cools to room temperature on the offload stage. Alternatively, the flip-chip semiconductor package 10 cools to a different temperature (which is lower than the temperature of the bond stage) as required while on the offload stage.

Preferably, the temperature of the offload stage may be controlled and varied as required for facilitating controlled cooling of the flip-chip semiconductor package 10. The cooling of the flip-chip semiconductor package 10 may be effected naturally. Alternatively, the cooling of the flip-chip semiconductor package 10 may be effected by forced convection cooling. For forced convection cooling, fluids, for example inert gases such as nitrogen, is pumped towards the flip-chip semiconductor package 10 for effecting the cooling thereof.

Alternatively, the flip-chip semiconductor package 10 may be transferred to one or more intermediate stage (not shown) before being transferred onto the offload stage. Preferably, the temperature of the intermediate stage is between the temperature of the bond stage 70 and the temperature of the offload stage. Further preferably, maintenance or control of the temperature of the intermediate stage facilitates controlled cooling of the flip-chip semiconductor package 10. Control of the cooling of the flip-chip semiconductor package 10 can be either manually or software controlled.

Although only the exemplary method 100 for fabricating a flip-chip semiconductor package provided by an embodiment is described above, a person skilled in the art will understand that various modifications to the steps, or the sequence thereof, of any one or more of the processes 200, 300, 400 and 500 may be made without departing from the scope of the present invention. A person skilled in the art will also appreciate that the steps of the method 100 represent steps in a general method for packaging a semiconductor component or device, for example semiconductor chips and transistors. In the exemplary method 100, the solder portions 20 of the bump structures 16 formed on the semiconductor chip 12 is maintained in the molten or liquid phase by thermal management of the bond tool 36. However, it will be appreciated by a person skilled in the art having the disclosure provided by the present description that the solder portions 20 of the bump structures 16 formed on the semiconductor chip 12 may alternatively be maintained in the solid phase prior to, and during the steps of 510 to 530 of the bonding process. In this case, the solder portions 20 of the bump structures 16 formed on the semiconductor chip 12 are melted during positioning of the semiconductor chip 12 at the bonding position in the step 540.

It will also be appreciated by a person skilled in the art with the disclosure provided by the present description that the exemplary method 100 for fabricating flip-chip semiconductor packages 10 enables accurate positioning of the bump structures 16 of the semiconductor chip 12 relative to the bond pads 64 of the substrate 22 during heating for reflow of the solder therebetween to thereby aid formation of accurate and reliable interconnects between the semiconductor chip 12 and the substrate 22.

Generally, semiconductor chips (and other semiconductor devices) have different coefficients of thermal expansion (CTE) as compared to substrates or carriers. Heating of materials with different CTEs results in differential thermal expansion thereof. Accordingly, the heating of the semiconductor chip 12 and the substrate 22 typically results in differential thermal expansion between the semiconductor chip 12 and the substrate 22. In a preferred embodiment of the present invention, pitch compensation occurs for the bond pads 64 of the substrate 22. The pitch compensation between the bond pads 64 of the substrate 22 is preferably calculated and determined for the offsetting differential thermal expansion between the semiconductor chip 12 and the substrate 22 due to their differential coefficients of thermal expansion (CTE) to thereby ensure accurate bonding, or interconnect formation, between the bump structures 16 of the semiconductor chip 12 and their corresponding bond pads 64 of the substrate 22. Further preferably, the pitch compensation between the bond pads 64 of the substrate 22 is performed for preventing electrical shorting between the interconnects formed. A partial diagrammatic overview of the pitch compensation of the bond pads 64 of the substrate 22 is shown in FIG. 15a and 15b. Alternatively, pitch compensation is performed between the bump structures 16 of the semiconductor chip 12. The pitch compensation between the bump structures 16 of the semiconductor chip 12 is preferably calculated and determined for offsetting differential thermal expansion between the semiconductor chip 12 and the substrate 22 due to their differential coefficients of thermal expansion (CTE).

Further alternatively, pitch compensation is performed for both the bump structures 16 of the semiconductor chip 12 as well as for the bond pads 64 of the substrate 22 for offsetting the differential thermal expansion between the semiconductor chip 12 and the substrate 22 due to their differential coefficients of thermal expansion (CTE).

The above described pitch compensation process or technique preferably ensures precise or near-precise bonding between the semiconductor chip 12 and the substrate 22, more specifically between the bump structures 16 of the semiconductor chip 12 and the bond pads 64 of the substrate 22, by the exemplary method 100. In addition, the above described pitch compensation process or technique preferably minimizes alignment or bonding offset between the semiconductor chip 12 and the substrate 22. A person skilled in the art provided with the disclosure of the present description will understand that the modifications to the pitch compensation process may also be done without departing from the scope of the present invention.

An exemplary system 600 or apparatus for packaging a semiconductor device or component, more specifically an exemplary system for fabricating the flip-chip semiconductor package 10 is also provided by the present invention. The exemplary system 600 is shown in FIG. 16.

The exemplary system 600 comprises means for performing the method 100 as described above. More specifically, the exemplary system 600 comprises means for performing any one or more of the steps 100 to 140 of the method 100, steps 210 to 280 of the process 200, steps 310 to 390 of the process 300, steps 410 to 450 of the process 400 and steps 510 to 560 of the process 500. The means referred to above are for example components, tools, elements or apparatuses, which are shaped and configured using techniques known to a person skilled in the art. For purposes of clarity and brevity, several key components of the system 600 will be further described below. It will however be appreciated by a person skilled in the art with the disclosure provided by the present description that this does not limit the scope of the system 600 covered by present invention.

As previously mentioned, the system 600 comprises means for performing the steps 210 to 280 of the process 200. Preferably, the system 600 comprises a semiconductor chip feeder gantry 602 used for facilitating the step 210 of providing the semiconductor chip 12.

The system 600 further comprises means for measuring thickness or height of the semiconductor chips 12. Preferably, measurement of the thickness or height of the semiconductor chips 12 is effected or facilitated by the chip pickup tool 24 and the encoder information as described above. It will however be appreciated by a person skilled in the art that alternative mechanisms may be used for measuring the thickness or height of the semiconductor chips 12.

The system 600 also comprises heating means, elements or devices for preheating the semiconductor chip 12 during the step 240 and for further heating the semiconductor chip 12 to the chip process temperature in the step 270. It is important to note that that the chip process temperature is preferably sufficient high enough to enable melting of solder portions 20 on the bump structures 16. Control and maintenance of the of at least one of the preheating and further heating of the semiconductor ship 12 is either software controlled or manually controlled using techniques known to a person skilled in the art.

In addition, the system 600 further comprises means for processing the substrate 22, or performing the steps 310 to 390, in the process 300. The system 600 preferably comprises a substrate feeder gantry 604 for providing the substrate 22 in the step 310.

The system 600 further comprises means for transferring flux 56 onto the substrate 22 in the step 320. As previously described, flux transfer may be performed by use of the tampon tool 60 for transferring flux 56 deposited on the flux transfer stage 58 onto the substrate 22. Alternatively, the system 600 can comprise other means or mechanisms for transferring flux 56 onto the substrate 22. Further alternatively, the system 600 comprises other means or mechanisms for transferring the no-flow underfill in place of flux onto the substrate 22.

The system 600 further comprises the substrate thickness measurement tool 74, as shown in FIG. 5h for measuring the thickness or height of the substrate 22. It will be understood by a person skilled in the art that alternative means or mechanisms may be used for measuring the thickness or height of the substrate 22.

The system 600 further comprises heating means, elements or device for preheating the substrate 22 in the step 350, and for further heating the susbtrate 22 to the substrate process temperature in the step 370. Preferably, the substrate 22 is heated by the bond stage 70 to the substrate process temperature. The bond stage 70 is designed and constructed for facilitating thermal management thereof, and of the substrate 22 positioned thereon. FIG. 17 and FIG. 18 show exemplary bond stage 70 designs. The bond stage 70 can comprise air pockets 606 for facilitating heat retention within (i.e. prevent heat dissipation from) the substrate 22. The bond stage 70 preferably comprises vacuum grooves 608. The vacuum grooves 608 facilitate application of vacuum or suction for securing the substrate 22 to the bond stage 70. The shape and position of the vacuum grooves 608 is predetermined so as not to coincide with positions of copper traces present on the substrate 22.

It is important that the system 600 is equipped and designed for thermal management of the each of the semiconductor chip 12 and the substrate 22 during the method 100. More specifically, the system 600 comprises means or mechanisms for thermal management of the semiconductor chip 12 and the substrate 22 during the exemplary bonding process 500. Thermal management may be facilitated by use of one or more of computer software programs and manual or mechanical input as known to a person skilled in the art. The system 600 preferably enables the solder portions 20 on the bump structures 16 to be maintained in the molten state before the semiconductor chip 12 is displaced towards the substrate 22 to thereafter enable bond formation between the bump structures 16 and the bond pads 64 of the substrate 22. The system 600 further comprises a water cooling mechanism 610 as shown in FIG. 19. The water cooling mechanism 610 comprises a pipe connector extension 612, a chiller plate 614, a substrate table base insulator 616, a hot plate 618 and a cartridge heater 620. Preferably, the water cooling mechanism 610 can be coupled to the bond stage 70 for at least one of facilitating insulation and cooling thereof. In other words, the water cooling mechanism 610 preferably facilitates thermal management of the bond stage 70.

It will be appreciated by a person skilled in the art that the system 600 further comprises means for performing the steps of the exemplary bonding process 500. Preferably, the system 600 comprises the second vision lens 38, also known as the look-up/look-down camera for aligning the semiconductor chip 12 relative the substrate 22 in the step 510 of the exemplary bonding process 500. More specifically, the second vision lens 38 facilitates accurate aligning of the bump structures 16 of the semiconductor chip 12 with reference to the bond pads 64 of the substrate 22. It will be understood by a person skilled in the art that alternative alignment means or mechanisms may be utilized by the system 600 for aligning the bump structures 16 formed on the semiconductor chip 12 with the bond pads 64 formed on the substrate 22.

In addition, the system 600 enables careful or accurate management of bond distance between the semiconductor chip 12 and the susbtrate 22. The system 600 comprises means for controlling at least one of speed and displacement magnitude of each of the first phase movement and the second phase movement of the bond tool 36 towards the bond stage 70 in the steps 520 and 530 respectively. Control or management of displacement magnitude of the bond tool 36 towards the bond stage 70 preferably depends on the actual stroke valve calculated by the exemplary formula shown in FIG. 10. In other words, the calculation of thickness or height of each of the semiconductor chip 12 and the substrate 22 enables management of the displacement magnitude of the bond tool 36 towards the bond stage 70 during the steps 520 and 530, as well as the bond distance between the semiconductor chip 12 and the substrate 22. Preferably, the displacement magnitude of the bond tool 70 towards the bond stage 70 during the steps 520 and 530 positions the bump structures 16 of the semiconductor chip 12 in contact with the bond pads 64 on the substrate 22. The system 600 further comprises means for offloading the formed flip-chip semiconductor package 10 during the step 140. As previously described, the flip-chip semiconductor package 10 is preferably cooled on the offload stage (not shown), As described above, it will be understood by a person skilled in the art that the system may comprise alternative cooling means and mechanisms may be used for cooling the formed flip-chip semiconductor package 10. For example, the system 600 can comprise a fluid system for effecting forced cooling of the flip-chip semiconductor package 20. Control of the cooling of the formed flip-chip semiconductor package 10 may be facilitated by use of at least one of computer software and manual or mechanical means as known to a person skilled in the art.

As previously mentioned, it will be understood by a person skilled in the art with the disclosure provided by the present description that the means, components or elements of the system 600 may be varied while still enabling performance of the steps 1 10 to 140 of the method 100. This is to say, the components, tools or apparatuses of the system 600 used for performing the steps of method 100 and the steps of each of the processes 200, 300, 400 and 500 may be varied, shaped, dimensioned and configured as required using techniques known to a person skilled in the art.

In the foregoing manner, an exemplary method 100 and system 600 for fabricating flip-chip semiconductor packages provided by the present invention is described. Various alterations or modifications to the exemplary method 100 and system 600 are also described above, and will be understood by a person skilled in the art to be within the scope of the present invention. It will also be understood by a person skilled in the art that the present invention is not limited to specific forms, arrangements or structures of the embodiments described above. It will be apparent to a person skilled in the art in view of this disclosure that numerous changes and/or modifications can be made without departing from the scope and spirit of the invention.