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Patent Searching and Data


Title:
3-STATE CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS6415821
Kind Code:
A
Abstract:

PURPOSE: To ensure the stable 3-state control with simple circuit constitution by setting a non-inverted logic circuit between two inverted logic circuits and setting a high impedance after an output is set at a high level.

CONSTITUTION: Both inverted circuits 1 and 2 have the same circuit constitution. A signal B is supplied to the circuit 2 and the output terminal 2-4 of the circuit 2 is set at '0'. Under such conditions, the 3-state control signal A of the circuit 1 is set at '1' and therefore the output terminal 1-4 of the circuit 1 is set at '0'. Then a current flows to a diode D3. As a result, the terminal 2-4 is set at '1'. At the same time, '0' of the terminal 1-4 is supplied to a non-inverted logic circuit 3 and the terminal 3-4 of the circuit 3 is set at '1' to cut off the current flowing to a diode D6. Thus the terminal 2-4 has a high impedance.


Inventors:
AZEGAMI KAZUO
MASUNAGA NAOHIRO
Application Number:
JP17221787A
Publication Date:
January 19, 1989
Filing Date:
July 09, 1987
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F3/00; G06F13/36; H03K19/00; H03K19/0175; (IPC1-7): G06F3/00; G06F13/36; H03K19/00
Attorney, Agent or Firm:
Sadaichi Igita