PURPOSE: To realize inexpensive constitution for the title method by providing a control signal generating part, a higher rank data control part, and a data selection part and performing the writing operations twice to a 32-bit I/O via a 16-bit bus CPU.

CONSTITUTION: A control signal generating part 8 is provided together with a higher rank data control part 5, and a data selection part 6. Then a 16-bit bus CPU 3 performs the writing operations twice to a 32-bit I/O 1 and also performs the reading operations twice to the I/O 1. When a writing operation is applied to a memory 4 from the I/O 1, 32 bits are written all at once. Then the CPU 3 reads the 32 bits at one time out of the memory 4. Therefore the data equivalent to 32 bits can be outputted at one time when the I/O 1 outputs the data received from the CPU 3 in two times to the outside. Then the DMA transfer is carried out to the memory 4 in 32 bits when the data received from outside are given to the CPU 3. Thus the CPU 3 performs its processing at the highest speed. Then the cost can be reduced in such a state where the CPU 3 does not need so fast processing although the I/O 1 needs the high-speed processing.