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Title:
4 QUADRANT MULTIPLIER
Document Type and Number:
Japanese Patent JPH02113382
Kind Code:
A
Abstract:

PURPOSE: To eliminate DC voltage offsets by constituting transistors connected with the form of a gilbert cell as multi-emitter transistors.

CONSTITUTION: The multi-emitter transistors with the same constitution are provided as the transistors T1-T4 and the respective emitters of the transistor T1 are connected to each emitter of the transistor T2 and the current input terminal of one controllable current source Is 21-22 altogether. Then, the current output terminal of the current source is connected to a reference potential (ground), a control input terminal is connected to a noninverted input terminal and the respective emitters of the transistor T3 are connected to each emitter of the transistor T4 and the current input terminal of one controllable current source Is 31-32 altogether. The current output terminal of the current source is connected to the reference potential (ground) and the control input terminal is connected to an inverted input terminal. Thus, the DC voltage offsets are eliminated.


Inventors:
RIHIARUTO SHIYUTETSUPU
Application Number:
JP22278189A
Publication Date:
April 25, 1990
Filing Date:
August 28, 1989
Export Citation:
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Assignee:
SIEMENS AG
International Classes:
G06G7/163; G06J1/00; H03C1/54; H03D1/22; H03D3/06; H03D13/00; (IPC1-7): G06G7/163; H03C1/54; H03D1/22; H03D3/06; H03D13/00
Attorney, Agent or Firm:
Tomimura Kiyoshi



 
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