Title:
7 level inverter device
Document Type and Number:
Japanese Patent JP6084691
Kind Code:
B2
Abstract:
It is composed of a three-phase three-level inverter 1, three single-phase five-level inverters 2, each of which is connected in series with an output of each phase of the three-phase three-level inverter 1, and pulse width modulation control means 8 provided for each phase which supplies gate pulses to the three-level inverter 1 and the single-phase five-level inverter 2 of the relevant phase. State transition means 84 which determines an output of a switching leg of the three-level inverter 1, and outputs of outside and inside switching legs of the single-phase five-level inverter based on transition of a voltage level created by the pulse width modulation control means 8, makes all of the three outputs of the three-level inverter 1, and the outside and inside switching legs of the single-phase five-level inverter 2 0 or positive, when the voltage level is positive, makes all of the outputs of these three legs 0 or negative, when the voltage level is negative, and makes all of the outputs of these three legs 0, when the voltage level is 0.
Inventors:
Toshiaki Oka
Application Number:
JP2015524917A
Publication Date:
February 22, 2017
Filing Date:
July 01, 2013
Export Citation:
Assignee:
Toshiba Mitsubishi Electric Industrial Systems Co., Ltd.
International Classes:
H02M7/483; H02M7/49
Domestic Patent References:
| JP2013021891A | 2013-01-31 | |||
| JP2006081361A | 2006-03-23 | |||
| JP2006081362A | 2006-03-23 | |||
| JP2000166251A | 2000-06-16 | |||
| JP2012085479A | 2012-04-26 | |||
| JP2013021891A | 2013-01-31 | |||
| JP2006081361A | 2006-03-23 | |||
| JP2006081362A | 2006-03-23 |
Foreign References:
| US20050065901A1 | 2005-03-24 |
Attorney, Agent or Firm:
Masanori Inoue