Title:
ABNORMAL SYNCHRONIZING SIGNAL ELIMINATION METHOD
Document Type and Number:
Japanese Patent JP3256493
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To detect only normal synchronizing signals by detecting specified pattern data from input data, judging them as synchronizing signals, when the detected synchronizing signals are provided with a periodicity while otherwise invalidating them.
SOLUTION: For input data, a synchronizing signal is detected through the use of a reproduction clock (s101). Whether or not the detected synchronizing signal is provided with a periodicity is inspected (s102), and returning to the start is performed when it is not provided with a periodicity and advancing to the next is performed, when it is detected successively for N times (N is an integer equal to or more than 1) (s103), and then it is proceeded to the next step. Then, whether or not identification(ID) information following the synchronizing signal is detected is inspected (s104), and when the ID value is a specified value, the synchronizing signal is defined. Furthermore, by using a window generated at a synchronizing signal position, whether or not the detected synchronizing signal is due to a burst error is inspected (s105). When the burst error is generated, it is invalidated. returning to the first is performed and detection is started. When it is not due to a burst error, it is recognized as a normal synchronizing signal (s106).
Inventors:
Gold pattern
Application Number:
JP22466698A
Publication Date:
February 12, 2002
Filing Date:
August 07, 1998
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
H04N5/93; G11B27/30; H04L1/00; H04L7/02; H04L7/08; H04N19/00; H04N19/44; H04N19/65; H04N19/70; H04N19/89; (IPC1-7): H04L1/00; H04L7/08; H04N5/93; H04N7/24
Domestic Patent References:
| JP6334644A | ||||
| JP57111810A | ||||
| JP4348631A | ||||
| JP2306472A | ||||
| JP8265169A | ||||
| JP5159474A |
Attorney, Agent or Firm:
Tadahiko Ito