Title:
ABNORMALITY DETECTING SYSTEM FOR PHASE LOCKED LOOP
Document Type and Number:
Japanese Patent JP3302513
Kind Code:
B2
Abstract:
PURPOSE: To provide the PLL abnormality detecting system with which out-of- synchronism, fluctuation of normal phase error and input clock abnormality can be detected, of which detection accuracy is not affected by the degradation of circuit characteristics, the deviation of elements and power source fluctuation and further, abnormality detecting sensitivity can be easily adjusted and changed.
CONSTITUTION: This system is constituted by providing abnormality detection point preparing circuits 11 and 12 for preparing a pair of abnormality detection points 1 and 2 before and after a synchronizing reference point by counting a VCO output clock with the synchronizing comparison point of an input clock as that reference, DFF 13 and 14 for latching and deciding the level of the input clock at the respective abnormality detection points 1 and 2, and OR gate 15 for deciding the abnormality of a PLL from the OR of the respective outputs of these DFF 13 and 14.
Inventors:
Satoshi Hisamatsu
Haruki Uchida
Haruki Uchida
Application Number:
JP19663994A
Publication Date:
July 15, 2002
Filing Date:
August 22, 1994
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
H03L7/095; H04L7/00; H04L7/033; (IPC1-7): H04L7/00; H03L7/095; H04L7/033
Domestic Patent References:
| JP645988A |
Attorney, Agent or Firm:
Toshiaki Suzuki (1 person outside)
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