To provide an absolute value operation circuit capable of attaining the absolute value operation of many bits at a high speed.

Input data are inputted to one input of an adder 11 through an inverter 12. A bit '0' is inputted to the other input of the adder 11 and a bit '1' is also inputted to the adder 11 as a carry input. A multiplexer output part 13 selects an output of the adder 11 or the input data. The output part 13 is constituted of AND circuits 13-1, 13-2 and an OR circuit 13-3. A selection signal is applied from a multiplexer selection part 14 to the output part 13. The MSB of the input data is used for the driving input of the selection part 14, which generates a selection signal for selecting the output of the adder 11 as output data when the MSB is '1' or the input data when the MSB is '0'. Consequently the influence of speed drop due to the increment of the number of operation bits can be suppressed.