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Patent Searching and Data


Title:
ACCESS CONTROL SYSTEM FOR DUAL PORT MEMORY
Document Type and Number:
Japanese Patent JP03074757
Kind Code:
A
Abstract:

PURPOSE: To attain the stable transfer of data between the CPUs of different processing speeds by inhibiting the read or the write for a CPU of the 'plural' side in terms of an area which is not written or read by a CPU of the '1' side.

CONSTITUTION: When the accesses are given to a CPU ('1' side CPU) of a short processing time from plural CPUs ('plural' side CPUs) of a long processing time and the data are written into or read out of a prescribed address of a DPM from the CPU of the '1' side, a flag is turned on only when a prescribed flag of the data on said address s kept OFF and the data are written or read out. Then the data are also read out or written only when the relevant flag of the data on the address is kept ON when either one of CPUs of the 'plural' side reads out or written into the prescribed address of the DPM. At the same time, the flag is turned off at the CPU side. As a result, an area which is not written by the CPU of the '1' side is never read out and an area which is not read out by the CPU of the '1' side is never written even though the CPUs of the 'plural' side have the random accesses.


Inventors:
Tsuzaki, Koichi
Okuzono, Keisuke
Sugiyama, Seiji
Shiwachi, Shinichi
Application Number:
JP1989000211038
Publication Date:
March 29, 1991
Filing Date:
August 16, 1989
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F15/167; G06F9/52; G06F13/18; G06F13/38; G06F15/16; G06F15/16; G06F9/46; G06F13/16; G06F13/38; (IPC1-7): G06F13/18; G06F15/16