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Title:
ACCESS CONTROLLER
Document Type and Number:
Japanese Patent JP01117543
Kind Code:
A
Abstract:

PURPOSE: To keep the impartiality by outputting an exclusive OR signal between an access address to be assigned and a signal on a 1st bus to a 2nd bus by each terminal equipment and stopping the transmission when discrepancy is detected with its own sent address signal on a 3rd bus.

CONSTITUTION: Assuming addresses assigned to terminal equipments 1, 2, 3 is 0000, 0001, 0010 respectively and the output of a random number generating circuit 4 from the leating point of time of a control signal 41 is 0101, the output of an exclusive OR circuit 3 of a terminal equipment 3 whose 3rd bit of the address is not 0 is logical 1, which represents the discrepancy. Thus, the terminal equipments 3 gives up the transmission request. The exclusive OR gate 15 outputs 1, 0 in the terminal equipments 1, 2 respectively. The terminal equipment recognizing the discrepancy gives up the transmission request and a terminale equipment 2 acquires the transmission right to the data bus 50. Since the reception priority of the transmission request depends on a random in this way, the impartiality of each terminal equipment is maintained.


Inventors:
Shimizu, Hiroshi
Application Number:
JP1987000276390
Publication Date:
May 10, 1989
Filing Date:
October 30, 1987
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04L12/40; H04L12/40; (IPC1-7): H04L11/00



 
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