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Patent Searching and Data


Title:
ACCESS SYSTEM FOR DYNAMIC RAM
Document Type and Number:
Japanese Patent JPS628246
Kind Code:
A
Abstract:

PURPOSE: To reduce an access time by using a logic address strobe and a physical address strobe as the timing of the line and row address strobes of a dynamic RAM.

CONSTITUTION: A high-order bit at a logical address 8 from a processor 1 is converted to a physical address 11 at an MMU2, and with being multiplexed with the low-order bit of the physical address 8 at the multiplexer 5 of a RAM control device 3, it is added to a dynamic RAM7 as a RAM address 13. A line address strobe control circuit 6 sends a line address strobe 10 to all of the dynamic RAMs by a logic address strobe 9 from the processor 1. A physical address strobe 12 from the MMU2 is sent to a decoder 4 with the high-order of the physical address, outputting one of row address strobes 14.


Inventors:
MIYAMOTO TSUNEHARU
Application Number:
JP14629185A
Publication Date:
January 16, 1987
Filing Date:
July 03, 1985
Export Citation:
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Assignee:
PANAFACOM LTD
International Classes:
G06F12/10; (IPC1-7): G06F12/10
Attorney, Agent or Firm:
Teiichi