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Title:
ACCESS SYSTEM OF MEMORY
Document Type and Number:
Japanese Patent JPS61115151
Kind Code:
A
Abstract:

PURPOSE: To suppress increase of the number of circuit devices and to attain the I/O processing of data by writing data corresponding to a high order address and shifting I/O data by the prescribed number of bits corresponding to a row or column to be read so as to execute the input and output.

CONSTITUTION: Where data is written on the 1st row of the 1st memory plane P1 in a picture memory 12, for instance, an address for indicating said writing is given to the picture memory 12 and a memory selector 13. A low-order address '1' given to the picture memory 12 sets the 1st bits of 16 memory elements ME1WME16 for comprising the picture memory 12 writable. Simultaneously, with the aid of the high-order address for specifying the 1st row, the memory selector 13 sets four memory elements ME1WME4 on the 1st rows in the picture memory 12 writable, while a data converter 14 outputs four data signals inputted from input terminals IT1WIT4 to lines DB1WDB4 of a data bus. Accordingly the 1st row of the 1st memory plane P1 is accessed. Thus a picture processing speed can be dramatically improved compared with a conventional system.


Inventors:
Hotta, Hideji
Suzuki, Osamu
Emi, Tetsukazu
Application Number:
JP1984000236927
Publication Date:
June 02, 1986
Filing Date:
November 09, 1984
Export Citation:
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Assignee:
SANYO ELECTRIC CO LTD
International Classes:
G09G5/36; G06F12/00; G06F12/06; G06T1/60; G09G1/02; G09G5/39; G11C7/00; (IPC1-7): G06F12/00; G09G1/02; G11C7/00



 
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