PURPOSE: To prevent the generation of a distortion near zero by setting (M+1) bit (M<N)-th from the high order of the memory means of an N bit (N is a natural number.) to '1' at the time of starting the accumulation and starting the accumulation.
CONSTITUTION: When a resetting signal RES comes to be '0', by a time slot 0, the output of AND gates 30∼34 comes to be all zero and the output of an OR gate 41 comes to be '1'. Thus, full adders 11∼16 output α0+128 and are latched to DFF21∼26. By a time slot 1, the signal RES comes to be '1' the AND gates 30∼34 and the OR gate 41 give outputs Y0∼Y23 of DFF21∼26 to the full adders 11∼16. For this reason, by the time slot 1, the calculation of α0+128+α1 is executed. Thus, the accumulation is successively executed, the calculation of a formula is executed by a time slot 63 and by the continuous time slot 0, the output is executed from the DFF21∼26. The DFF27∼29 latch the high order 16 bit of the data by a clock signal CK2 and the output of the accumulator is obtained.
NURIYA KOZO
TANI YASUNORI
| JPS5970308A | 1984-04-20 | |||
| JPS59176919A | 1984-10-06 |