Title:
ACTIVE MATRIX TYPE TFT ELEMENT ARRAY
Document Type and Number:
Japanese Patent JP3019047
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To suppress a decrease in yield without increasing the number of production stages by disposing amorphous silicon semiconductor films at a length below the spacings between drain wirings to an island shape on gate wiring between adjacent pixel electrodes in a drain wiring direction.
SOLUTION: The amorphous silicon semiconductor films 4c of the same layer as the amorphous silicon semiconductor films constituting amorphous silicon thin-film electric field effect type transistors are disposed at the length below the spacing of the drain wirings to the island shape on the gate wiring 2 between the adjacent pixel electrodes 8a, 8b in the drain wiring direction. In such a case, projecting parts are formed by disposing the amorphous silicon between the adjacent pixel electrodes 8a, 8b in the drain wiring direction. Even if the remaining of the photoresist film occurs at the time of patterning of indium tin oxide(ITO) films constituting the pixel electrodes 8a, 8b, the photoresist film hardly remains on the projecting parts and, therefore, the short- circuit of the adjacent pixel electrodes 8a, 8b is prevented.
Inventors:
Takuya Kato
Application Number:
JP32216197A
Publication Date:
March 13, 2000
Filing Date:
November 07, 1997
Export Citation:
Assignee:
NEC
International Classes:
G02F1/136; G02F1/1368; (IPC1-7): G02F1/1365
Domestic Patent References:
| JP62205390A |
Attorney, Agent or Firm:
Asamichi Kato