Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
ACTIVE WAFER LEVEL CONTACTING SYSTEM
Document Type and Number:
Japanese Patent JPH10150080
Kind Code:
A
Abstract:

To make impedance matching and the minimum parasitic capacitance accurate and to restrict the distortion of the performance characteristics of the device under test by arranging the active-wafer plane contact system having a part of signal adjustment or active-wafer plane contact system on a wafer in an integrated circuit testing system.

A wafer-plane contact system 20 is arranged on an under test wafer 22. The wafer-plane contact system 20 mounts an active silicon wafer 34. Then, the active silicon wafer 34 is electrically connected to a tester 26, and the testing signal between the tester 26 and a contact element 60 is adjusted. Furthermore, the active silicon wafer 34 has a contact region 50, active component regions 52 and 54, a connecting pad region 56 and a connecting pad region 58. The active component regions 52 and 54 are made to be the active components such as a testing circuit of a signal adjusting circuit.


Inventors:
Erik, Klein V.
Application Number:
JP1996000302124
Publication Date:
June 02, 1998
Filing Date:
November 13, 1996
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
JOHNSTECH INTERNATL CORP
International Classes:
G01R31/28; H01L21/66; (IPC1-7): H01L21/66; G01R31/28
Attorney, Agent or Firm:
恩田 博宣