PURPOSE: To obtain a data of (N-α)-bit close to a true value by adding the α-th bit data in N-bit AD data to data of high-order (N-α)-bit data.

CONSTITUTION: A latch 9 fetching an N-bit data whose conversion is finished, an adder 10 adding the α-bit to the high-order (N-α)-bit of the N-bit data, and a shift register 11 of the (N-α)-bit fetching the result of arithmetic operation are provided. Moreover, the adder 10 inhibits the addition when the data of the high-order (N-α)-bit is all '1'. When the α-bit of the N-bit AD data is added to the data of high-order (N-α)-bit, the data of the (N-α)-bit obtained is in a form of rounding off the N-bit data at the α-th bit. Thus, the data of (N-α)-bit with higher accuracy and close to a true value more than the (N-α)-bit data omitted the figures below the α-th bit simply is obtained.