Title:
適応等化回路
Document Type and Number:
Japanese Patent JP3611472
Kind Code:
B2
Abstract:
High-order partial response equalization is performed so that the equalization error of an input signal having non-linear distortions is minimized, thereby improving the characteristics of a reproduced signal. An input signal is subjected to high-order partial response equalization adapted to a non-linear distortion waveform by using a transversal filter 3; a provisional equalization target value is estimated by a provisional decision circuit 4; an error between the provisionally decided value and the input signal is detected by an error detection circuit 5; an error between the provisionally decided value and the output signal from an A/D converter 1 is detected by an input distortion detection circuit 7; the error outputted from the error detection circuit 5 is monitored by an output distortion detection circuit 6; the equalization target value is controlled by an equalization target control means 8 so that the equalization error is minimized; and tap coefficients are controlled by a tap coefficient control means 10.
Inventors:
Toshinori Okamoto
Yoichi Ogura
Yoichi Ogura
Application Number:
JP2542399A
Publication Date:
January 19, 2005
Filing Date:
February 02, 1999
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G11B20/10; G11B20/18; H03H15/00; H03H21/00; H04B3/06; H04L25/03; H04L25/497; (IPC1-7): G11B20/10
Domestic Patent References:
| JP10320918A | ||||
| JP10106158A | ||||
| JP9153257A | ||||
| JP9097476A | ||||
| JP10275422A | ||||
| JP7240068A |
Attorney, Agent or Firm:
Kenichi Hayase