To increase the number of taps and improve reception performance by suppressing an increase in circuit scale and an increase in operating clock frequency.

A first block-generating section 102 divides an input signal in the time domain into blocks. A second block-generating section 128 divides an error signal into blocks. A third clock-generating section 131 divides a decision feedback signal into blocks. A first FFT section 104 fast-Fourier-transforms the input signal for each block. A fourth FFT section 130 fast-Fourier-transforms the error signal for each block. A fifth FFT section 133 fast-Fourier-transforms the decision feedback signal for each block. A block control section 101 controls so that the block size when the feedback signal is divided into blocks is shorter than the block size when the input signal is divided into blocks, and the block size when the feedback signal is divided into blocks becomes a length according to the number of taps in adaptive equalization processing.