Title:
ADAPTIVE EQUALIZING CIRCUIT
Document Type and Number:
Japanese Patent JP3928332
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To realize a stable adaptive equalizing operation without varying a reference value for calculating an equalization error to an input fluctuating in amplitude, in an adaptive equalizing circuit.
SOLUTION: An input signal is sampled and held by a timing signal a half cycle out of phase with a reference signal for the input signal. The circuit calculates an equalized output from the obtained sample data, and calculates a difference of only the first output value after zero-crossing from an arbitrary set reference value and uses it as an equalized error, and updates a coefficient of the adaptive equalizing circuit from the equalized error and the sample data. Moreover, to a symmetry displacement of the input signal, the reference value of the adaptive equalizing circuit is made to vary synchronizing with variation in the binarized threshold value of a subsequent-stage binarization circuit of the adaptive equalizing circuit.
Inventors:
Koichiro Nishimura
Hirose Koichi
Hirose Koichi
Application Number:
JP2000143398A
Publication Date:
June 13, 2007
Filing Date:
May 11, 2000
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
G11B20/10; H03H15/00; H03H21/00; H04B3/06; H04L25/03; (IPC1-7): G11B20/10; H03H15/00; H03H21/00; H04B3/06
Domestic Patent References:
| JP11259986A | ||||
| JP9321671A | ||||
| JP9073726A |
Attorney, Agent or Firm:
Manabu Inoue