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Patent Searching and Data


Title:
ADDER CIRCUIT
Document Type and Number:
Japanese Patent JPS6259412
Kind Code:
A
Abstract:

PURPOSE: To obtain an adder output and to compress/expand the time axis by giving clocks of opposite phase to two CCDs, extracting the output at each 1/2 clock to eliminate the clock and changing the clock frequency.

CONSTITUTION: Two kinds of signal waveforms (a), (b) are inputted to the CCDs 3, 4 through input terminals 1, 2. Clocks of opposite phase are fed to the CCDs 3, 4 from a clock generator 5. The outputs are switched by a switch 6 at each 1/2 clock to obtain an output of waveform (e). The clock component included in the waveform (e) is eliminated by an LPF 7 to obtain an adder signal of then two input signals. Further, the time companding is attained simultaneously by changing the clock frequency from the generator 5 given to the CCDs 3, 4.


Inventors:
IKUHARA HIDEYUKI
Application Number:
JP19974285A
Publication Date:
March 16, 1987
Filing Date:
September 10, 1985
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H04N7/01; G06G7/14; H03K4/00; H03K5/04; (IPC1-7): G06G7/14; H03K4/00; H03K5/04; H04N7/01
Attorney, Agent or Firm:
Toshio Nakao