PURPOSE: To shorten the delay time of a critical path where a carry is propagated and speed up arithmetic by providing a logic circuit which makes the delay time of the least significant digit carry propagation path of CLA cells in a 1st and a 2nd stage layer shorter than the delay time of CLA cells of a 3rd stage.

CONSTITUTION: In addition to a carry function generator 1, block carry function generators 100-115, and 200-203, and the CLA cell 300 in the 3rd stage layer, and a sum generator 2, this circuit is equipped with the CLA cells 400A-403A of the 2nd stage as 2nd type CLA cells and CLA cells 500A-515A of the 1st stage layer. The 2nd type using a two-input NAND gate is shorter in the delay time from the input of a carry input Cin from a low order layer to the acquisition of a carry output to a high-order layer and faster than a 1st type CLA cell which uses a 4-input NAND gate. Therefore, the 2nd type CLA cells are used for the 1st and 2nd stage layers to reduce the delay of the carry input to the lowest order block and the operation is speeded up.