PURPOSE: To obtain one-fold and two-fold addition results of an addend at a faster speed by constituting an adding circuit and a register circuit in double constitution for two-fold and one-fold adding operations of the given addend.

CONSTITUTION: The 1st register circuit 3 inputs the output (b) of the 1st adder 1 with the leading edge of a clock signal CK and sends out an output (d). The 2nd register circuit 4 sends out the output (c) of the 2nd adder 2 as an output (e) when the clock signal CK is at a low level and holds and sends out the output (c) of the adder 2 right before the clock varies from the low level to a high level when the clock is at the high level. A selecting circuit 5 selects the output (e) of the register circuit 4 when the clock signal CK is at the high level and the output (d) of a register circuit 3 when the clock signal is at the low level, outputting an addition result signal (f). Thus, addition is performed according to the clock signal CK and values which are equal to and twice as large as an addend signal (a) are obtained as the addition result output signal (f).