PURPOSE: To exercise easily address control differing in the number of address buses by setting easily the boundary of address buses by controlling bus addresses by a program, by cascading several address registers with connected addresses.

CONSTITUTION: Address registers 71W7n are cascaded and carry output terminal CA and borrow output terminal BR of the lowest-order register 71 are connected to those of post-stage register 72. After the completion of the execution of instructions according to a microprogram in buses access, access to the boundary of address buses is attained and operation code OP is decoded by decoding circuit 6; and an instruction to count the bus address by +1 or -1 is sent out; and a carry or borrow signal is given to registers 71W7n and a carry or borrow signal is outputted from the highest-order register 7n to set flip-flop 8 or 10, so that a processing routine will be interrupted by its output.