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Patent Searching and Data


Title:
INPUT/OUTPUT ADDRESS CONVERSION CIRCUIT AND COMPUTER SYSTEM
Document Type and Number:
Japanese Patent JPH03123949
Kind Code:
A
Abstract:

PURPOSE: To permit a computer system to share a program even if the input/ output addresses differ when I/O to be used is the same by providing RAM converting the addresses and FF controlling the state of RAM or the like.

CONSTITUTION: RAM 50 in an input/output address conversion circuit 14 inputs the input/output address 41 by the state control of FF52, converts written data and outputs the converted input/output address 44. At that time, conversion address data can be set to the input/output address for controlling the state of FF52 by writing conversion address data for the specified address of RAM 50, which a decoder 51 specifies. Consequently, the computer system can share program and I/O as an enlargement system can be used instead of I/O as a basic system even in the input/output addresses differ when I/O to be used are the same since the input/output address for I/O can arbitrarily be redefined.


Inventors:
KUBOTA KAZUMI
Application Number:
JP26000289A
Publication Date:
May 27, 1991
Filing Date:
October 06, 1989
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G06F13/14; (IPC1-7): G06F13/14
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)