PURPOSE: To extend the logical address without a complicated constitution, by selecting one of the logical address before conversion and a real address after conversion, depending whether the logical address is within a specified range or not.
CONSTITUTION: An upper-order prescribed bit of a logical address set to a logical address register 1 is checked at a zero check circuit 2 and each bit is not zero, then it is discriminated as the logical address at a prescribed value of MB or over and an output of the circuit 2 goes to logical 1. Thus, an output (c) of a control circuit 5 goes to logic (1, 0) independently of the output of a comparison circuit 4 whether or not the logical address exists in a TLB and an output in response to an address conversion program from a register 8 and controls a selection circuit 6. Then, the subordinate bit of the logical address of the register 1 is selected as a converted real address. Then, the extension of the logical address is executed without complicated constitution and overhead.
| JPH04213138 | INFORMATION PROCESSOR |
| WO/2014/084150 | INFORMATION PROCESSING APPARATUS, CONTROL METHOD THEREOF, AND PROGRAM |
| JPS5794993 | MICROPROGRAM CONTROLLER |
KAWABE TAKASHI
NAGASHIMA SHIGEO
