PURPOSE: To increase the processing speed of an address converting device by using a latch circuit and a multiplexer to form an address converter circuit which performs the conversion between two addressing ways for both feedforward and feedback operations in a weight memory of a neural net.

CONSTITUTION: A layer 0-20 and a 1-25 of a neural network consist of 2n(n=2) and 2m(m=1) pieces of neurons respectively. A weight memory 2 records the weight Wij. When a 1st address is inputted to an address bus 8, a selection signal line 9 is set at an L level and the 1st address is outputted as it is. Meanwhile the line 9 is set at an H level when a 2nd address is inputted to the bus 8 and the corresponding 1st address is outputted. A latch circuit 7 designates the nuron of the layer 0-20. That is, the circuit 7 outputs a fixed address when the line 9 is kept at an H level. A multiplexer 6 is provided at a position set by shifting the 2nd address by (n) bits in the higher rank direction.