Title:
ADDRESS RESIGNATION METHOD FOR PICTURE MEMORY
Document Type and Number:
Japanese Patent JPS6481569
Kind Code:
A
Abstract:
PURPOSE:To decrease number of digits of each means more than the case of direct supply of original address information by dividing the original address information into high-order bit information and low-order bit information and giving one of them to a multiplication means and an adder means. CONSTITUTION:The X address information Xad and the Y address information Yad are divided into the information comprising the high-order bit and the information comprising the low-order bit and a product between the divided high-order address information Yad(8-14) and the constant K decided separately is obtained by a multiplication means 1. A linear address Lad(0-28) is obtained by combining the output of the adder means 2 adding the output and the X address information Xad(8-14), and the divided low-order Y address information Yad(0-7) and the low-order X address information Xad(0-7) in parallel and the address of the picture memory is designated based on the linear address.
More Like This:
Inventors:
TAKIZAWA TSUTOMU
Application Number:
JP23728487A
Publication Date:
March 27, 1989
Filing Date:
September 24, 1987
Export Citation:
Assignee:
SHAKEN KK
International Classes:
B41J2/44; B41J2/485; B41J3/00; G06F12/02; G06K15/12; G06T1/20; G06T1/60; H04N1/21; (IPC1-7): B41J3/00; B41J3/12; G06F15/64; G06K15/12; H04N1/21
Domestic Patent References:
| JP45014986A | ||||
| JPS5439098A | 1979-03-24 |
Attorney, Agent or Firm:
Hiroaki Tazawa (2 outside)