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Patent Searching and Data


Title:
ADDRESS STOP SYSTEM
Document Type and Number:
Japanese Patent JPS59106057
Kind Code:
A
Abstract:

PURPOSE: To set an optional number of stop addresses in all of the address space of a microprocessor, by providing a means which compares the stop address from a storage address and the address from a microprocessor with each other.

CONSTITUTION: A counting circuit 10 outputs repeatedly an address d1Wd4, where a count output (f) is stored, synchronously with a clock signal (e). The output (f) is transmitted to a stop address memory 9, and a stop address b1W b4 stored in the address d1Wd4 is outputted as a memory output (h) and is transmitted to a comparing circuit 13. The circuit 13 compares an address (a) with the output (h)=b1Wb4 from the memory 9 with each other, and the circuit 13 sets an output (i) to (1) when they coincide with each other. An effective signal (j) outputted to a control signal bus 7 is set to (1) during the time when the address (a) is effective. As the result, a gate 14 outputs a stop signal (c) synchronously with the output (i) and transmits it to a processor 4 through a data bus 8. The processor 4 stops the operation after transmitting the stop address and is held in the state at this time.


Inventors:
KATOU MASARU
ISHIBASHI MASAAKI
SHIYOUJI MASAHIKO
Application Number:
JP21641282A
Publication Date:
June 19, 1984
Filing Date:
December 10, 1982
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F11/28; G06F11/36; (IPC1-7): G06F11/28
Attorney, Agent or Firm:
Koshiro Matsuoka