PURPOSE: To decrease the number of pins of flip-flops by providing terminals which are as many as the larger number of bits between the row address and column address of a dynamic RAM and 1st storage means, and inputting the outputs of 2nd storage means 2 which are as many as the smaller number of bits to the 1st storage means.

CONSTITUTION: The terminals 2 which are as many as the larger number (n) of bits between the row address and column address of the dynamic RAM 9 and the 1st storage means 3 and 4 which are connected to them are provided. Further, the 2nd storage means 5 which are as many as the smaller number (m) of bits are provided. Further, a central processing unit 1 equipped with a mechanism 6 which inputs the outputs of the 2nd storage means 5 to the 1st storage means 3 at next timing is provided and a control part 8 accesses the dynamic RAM 9 according to the address outputted from the terminal 2.