PURPOSE: To provide the I/O address translation system with a simple and inexpensive circuit configuration and high expandability and versatility.

CONSTITUTION: A processor (not shown by figure) connected to an address bus 1 and a data bus 2 preliminarily stores information for operating an I/O address translation in an I/O map 4a in an address translation information holding means 4 by an I/O write access. Afterwards, the processor performs an access to an I/O address space to be translated and the information for operating the address translation is read from the I/O map 4a by the control of an address translation control means 3 so that the I/O address translation can be executed based on the information.