Title:
ADDRESSING SYSTEM OF ELECTRONIC COMPUTER
Document Type and Number:
Japanese Patent JPS5922151
Kind Code:
A
Abstract:
PURPOSE: To double addresses of a storage device which can be specified by a program, by providing a flip-flop circuit which discriminates between instruction words and data words of the program automatically.
CONSTITUTION: The FFC is so set that an instruction word block MI is operated as an initial state. Then, every time a demand for data transfer to and from the data word block MO rises, the FFC is inverted to operate the MO. The FFC is retarned to the initial state after the data transfer is completed. At this time, an address register R specifies an address in the storage device and has bits as many as internal data bits of the electronic computer.
Inventors:
YASUMI YASUMASA
Application Number:
JP13163482A
Publication Date:
February 04, 1984
Filing Date:
July 28, 1982
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G06F9/32; G06F9/38; G06F12/06; (IPC1-7): G06F13/00
Attorney, Agent or Firm:
Shinichi Kusano
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