Title:
AGC CIRCUIT
Document Type and Number:
Japanese Patent JP3223227
Kind Code:
B2
Abstract:
PURPOSE: To provide the AGC circuit which doesn't degrade the decoding characteristic of a correlation detector by operating the AGC loop synchronously with the symbol clock obtained from the correlation detector.
CONSTITUTION: When the level of the signal inputted from an input terminal 10 is changed, a detection voltage 14 is changed, and the difference between this voltage 14 and a reference voltage 15 is outputted as a control voltage 18 by a level comparator 16 and is inputted to a sampling and holding circuit 17. Meanwhile, the output signal of a gain control amplifier 11 is inputted to an orthogonal demodulator 19 and is demodulated to an I signal 24 and a Q signal 25, and they are converted to digital signals by A/D converters 20 and 21 and are inputted to a correlation detector 22, and detection of the correlation value in one symbol time and reproducing of a symbol clock 23 are performed. The control voltage 18 as the output of the level comparator 16 is sampled/held synchronously with the symbol clock 23 generated in this manner, and the gain control amplifier 11 is controlled based on this sampling/holding.
Inventors:
Manabu Yamaguchi
Application Number:
JP14300994A
Publication Date:
October 29, 2001
Filing Date:
June 24, 1994
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H03G3/20; (IPC1-7): H03G3/20
Domestic Patent References:
| JP5122180A | ||||
| JP583059A | ||||
| JP4239808A | ||||
| JP661767A |
Attorney, Agent or Firm:
Mitsutake Murayama