SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF

Title:

SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF

Document Type and Number:

Japanese Patent JPH0786332

Kind Code:

A

Abstract:

PURPOSE: To improve reliability of plating bonding in irregularity of height direction of an inner lead by a method wherein a plurality of electrode pads are short-circuited by wiring pattern, and the potential from the lead terminal which is brought into contact with the electrode pads is applied to non-contact electrode parts too.

CONSTITUTION: The electrode pads 12 of a semiconductor chip 11 is short- circuited by a wiring pattern 11a. When the semiconductor chip 11 and a lead frame 13 are adhered, at least one of lead terminals 14 is brought into contact with one of the electrode pads 12. As a result, uniform potential can be applied to each electrode pad of the semiconductor chip 11 from the lead terminals 14 when a plating-bonding operation is conducted. Accordingly, potential is applied to each electrode pad 12 when a plating-bonding operation is conducted, highly efficient plated junction can be formed by the growth of a metal-plated layer 15 from both lead terminals 14 and the electrode pad 12, and the reliability of plating bonding can be improved.

Inventors:

SHIMIZU SHINYA
OTAKI HIROKO
TSUKAMOTO TAKETO
TOKI SOTARO

Application Number:

JP23188893A

Publication Date:

March 31, 1995

Filing Date:

September 17, 1993

Export Citation:

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Assignee:

TOSHIBA CORP
TOPPAN PRINTING CO LTD

International Classes:

H01L21/60; H01L23/50; (IPC1-7): H01L21/60; H01L23/50

Attorney, Agent or Firm:

Takehiko Suzue

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