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Title:
ALARM DETECTION SYSTEM ON TIMING EXTRACTION SYSTEM USING PHASE LOCK LOOP CIRCUIT
Document Type and Number:
Japanese Patent JPS54158899
Kind Code:
A
Abstract:

PURPOSE: To detect abnormality accurately by attaching an alarm detection circuit which generates an alarm signal when a PLL circuit is not locked or when reception of a signal is interupted.

CONSTITUTION: In the timing extraction system using a PLL circuit, signal (f) differentiated by the input of phase comparator PC24 is expanded in pulse expander circuit 31 by one bit of the repetitive frequency of voltage control oscillator 28 and signal in case of coincidence with another input (g) of PC24 is extracted by FF circuit 32 and then pulse-expanded by pulse expander circuit 33 to obtain an alarm signal, thereby detecting an unlocked state. At every time when the change point of received signal (a) is detected, pulses are expanded by pulse expandar circuit 35 and when the output is OFF, an alarm signal is sent out, thereby detecting the state when the received signal is intermitted. Two alarm detection circuits added make it possible to detect abnormality accurately.


Inventors:
NAKAMURA YOSHIHIRO
MIZUKOSHI TATSUO
Application Number:
JP6717578A
Publication Date:
December 15, 1979
Filing Date:
June 06, 1978
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G08B25/00; G08B23/00; (IPC1-7): G08B23/00; G08B25/00



 
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