To provide an alarm informing circuit effective for lowering of a voltage level in a main electric power source.

A CPU 4 stops supply of an electric power source to a transmitting part 7 when the CPU 4 receives an alarm signal #1 output from a voltage detecting circuit 15. Information in the other communication party is displayed on a LCD 6 at the same time. The CPU 4 gains a displaying time setting data to be set in a counter 17. A DC/DC converter 12 and a regulator 13 are provided between a spare battery 14 and a main electric power source 2, and the spare battery 14 is charged all the time when a terminal device is operated normally. A spare battery voltage monitoring circuit 18 for monitoring a voltage level of the spare battery 14 is provided to stop forcibly the supply of the electric power source to the LCD CONTR/DRV 5.