Title:
３次元回路デバイス向けの導電性チャネルのための酸化アルミニウムランディング層
Document Type and Number:
Japanese Patent JP6442735
Kind Code:
B2
Abstract:
A multitier stack of memory cells having an aluminum oxide (AlOx) layer as a noble HiK layer to provide etch stop selectivity. Each tier of the stack includes a memory cell device. The circuit includes a source gate select polycrystalline (SGS poly) layer adjacent the multitier stack of memory cells, wherein the SGS poly layer is to provide a gate select signal for the memory cells of the multitier stack. The circuit also includes a conductive source layer to provide a source conductor for a channel for the tiers of the stack. The AlOx layer is disposed between the source layer and the SGS poly layer and provides both dry etch selectivity and wet etch selectivity for creating a channel to electrically couple the memory cells to the source layer.
Inventors:
Shu, Hong Bin
Haller, Gordon
Simsek-Ege, Fatoma
Haller, Gordon
Simsek-Ege, Fatoma
Application Number:
JP2016570091A
Publication Date:
December 26, 2018
Filing Date:
June 26, 2015
Export Citation:
Assignee:
INTEL CORPORATION
International Classes:
H01L27/11556; H01L21/336; H01L27/10; H01L27/11524; H01L29/788; H01L29/792
Foreign References:
| US20100109065 | ||||
| US20140193969 |
Attorney, Agent or Firm:
Longhua International Patent Service Corporation