Amorphous oxide semiconductor membrane transistor manufacturing method

Japanese Patent JP5917679

B2

This disclosure provides systems, methods and apparatus for fabricating thin film transistor devices. In one aspect, a substrate having a source region, a drain region, and a channel region between the source region and the drain region is provided. The substrate also includes an oxide semiconductor layer, a first dielectric layer overlying the channel region, and a first metal layer on the dielectric layer. A second metal layer is formed on the oxide semiconductor layer overlying the source region and the drain region. The oxide semiconductor layer and the second metal layer are treated to form a heavily doped n-type oxide semiconductor in the oxide semiconductor layer overlying the source region and the drain region. An oxide in the second metal layer also can be formed.

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Kim, Jung Hong
Hong, John Huntul
Bread, yorin

JP2014501137A

May 18, 2016

March 12, 2012

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QUALCOMM MEMS Technologies, Inc.

H01L21/336; G09F9/30; H01L21/28; H01L29/786

JP2011228622A
JP2012015436A
JP2008205469A
JP2010219094A
JP2007318112A
JP2008166724A
JP2005175121A
JP2011523080A
JP2007284342A
JP2009278115A

WO2009120558A1

Kurata Masatoshi
Yoshihiro Fukuhara
Makoto Nakamura
Nobuhisa Nogawa
Takashi Mine
Naoki Kono
Katsu Sunagawa
Morisezo Iseki
Takao Ako
Tadashi Inoue
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi

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