Title:
AMPLIFICATION CIRCUIT
Document Type and Number:
Japanese Patent JPS62290206
Kind Code:
A
Abstract:
An amplifier arrangement for reducing an unwanted d.c. offset of an amplitude-varying input signal, comprising a threshold circuit (A3, B3) and an amplifier stage (A1, B1) coupled thereto, which threshold circuit (A3, B3) is provided with a bistable trigger circuit (A4, B4). This bistable trigger circuit (A4, B4) reduces the d.c. level of the input signal or output signal of the amplifier stage (A1, B1) in a steplike manner when this d.c. level increases. The bistable trigger circuit (A4, B4) has a hysteresis which is larger than the maximum amplitude variation of the input signal as a result of the desired signal component, so that a linear amplification of this desired signal component is possible and, in the case of a non-varying d.c. level, variations of the input signal due to the desired signal component cannot give rise to a d.c. reduction. This amplifier arrangement may be used in a phase-locked loop of a directly mixing synchronous AM receiver, which phase-locked loop is used for generating a synchronous local carrier in order to increase the input dynamic range of the receiver.
Inventors:
ENGERU ROZA
Application Number:
JP12412987A
Publication Date:
December 17, 1987
Filing Date:
May 22, 1987
Export Citation:
Assignee:
PHILIPS NV
International Classes:
H03F3/34; H03G3/20; H03L7/093; (IPC1-7): H03F3/34; H03L7/08
Domestic Patent References:
| JPS51120659A | 1976-10-22 | |||
| JPS58171108A | 1983-10-07 |
Attorney, Agent or Firm:
Akihide Sugimura