Document Type and Number:
Japanese Patent JP2007243491
Kind Code:
A
Abstract:
To provide an amplifier circuit which easily suppresses an intermodulation distortion signal that is caused by amplification.
In a path of a first amplifier 102, the first amplifier 102 applies class A amplification to an input signal and amplifies the input signal by a multiple of α. As a result, input signal components F1, F2with a power αF and intermodulation distortion signal components (2F1-F2) and (2F2-F1) with a power Fk1are produced. In a path of a second amplifier 103, the second amplifier 103 applies class AB amplification to the input signal, and amplifies the input signal by a multiple of β(α>β). As a result, input signal components F1, F2with a power βF and intermodulation distortion signal components (2F1-F2) and (2F2-F1) with a power Fk2are produced. Finally, a composite unit 104 composes: the input signal components F1, F2with the power αF, and the intermodulation distortion signal components (2F1-F2) and (2F2-F1) with the power Fk1, in a positive phase; and the input signal components F1, F2with the power βF, and the intermodulation distortion signal components (2F1-F2) and (2F2-F1) with the power Fk2, in an opposite phase.
COPYRIGHT: (C)2007,JPO&INPIT
Inventors:
TSUCHIYA ETSUO
SUEISHI TOSHINORI
OBANA RIICHIRO
Application Number:
JP2006061897A
Publication Date:
September 20, 2007
Filing Date:
March 07, 2006
International Classes:
H03F1/32
Domestic Patent References:
| JPH04217103A | 1992-08-07 | | | |
| JP2003198273A | 2003-07-11 | | | |
| JP2002064201A | 2002-02-28 | | | |
Attorney, Agent or Firm:
Shiro Nakajima
