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Title:
AMPLITUDE LIMITING OSCILLATOR CIRCUIT
Document Type and Number:
Japanese Patent JPS54148462
Kind Code:
A
Abstract:

PURPOSE: To ensure the stable operation with a small amplitude for the oscillator circuit by connecting one of the differential paired transistors featuring the different balancing states to each other to the positive feedback loop and then connecting the other transistor to the negative feedback loop respectively.

CONSTITUTION: One side of differential paired transistors TRQ1 and Q2 plus TRQ3 and Q4 are connected to form the positive feedback loop, and the other side are connected to form the negative feedback loop respectively. At the same time, the emitter area ratio is set to 1:N (N>1) between TRQ3 and Q4. Thus, the emitter current features 1:N with a lower gain obtained than the differential amplifier featuring the equal emitter current. In other words, the gain becomes maximum when the base bias features the unbalanced state with the equal emitter current as shown by broken-line curve G2. Accordingly, the composite gain features solid-line curve G3, obtaining a stable amplitude limiting oscillator featuring a small amplitude. Furthermore, the oscillation width can be set freely by selecting the value of N.


Inventors:
KUSAKABE HIROMI
Application Number:
JP5740578A
Publication Date:
November 20, 1979
Filing Date:
May 15, 1978
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H03B5/04; H03B5/12; H03L1/02; (IPC1-7): H03B5/04; H03B5/08



 
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