Title:
ANALOG ARITHMETIC CIRCUIT
Document Type and Number:
Japanese Patent JPS5852776
Kind Code:
A
Abstract:
PURPOSE: To reduce an error of an output current as an analog arithmetic result due to the relation between an input current and a bias current, by setting the collector current of a transistor (TR) to a constant current value through a current mirror circuit.
CONSTITUTION: An arithmetic circuit is equipped with the 1stW6th TRs Q1WQ6. The TRs Q5 and Q4 receiving bias currents I2 at their collectors constitute a current mirror circuit 11, and the collector current of the TRQ4 is set to a specified current value through the current mirror circuit 11, thereby reducing an error of an output current as an analog arithmetic result due to the relation of an input current and the bias current I2.
Inventors:
NAGANO KATSUMI
Application Number:
JP15127481A
Publication Date:
March 29, 1983
Filing Date:
September 24, 1981
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
G06G7/20; H03F3/343; H03F3/45; (IPC1-7): G06G7/20
Attorney, Agent or Firm:
Takehiko Suzue
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